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w78e054d/w78e052d/w78e051d data sheet 8-bit microcontroller publication release date: oct 20, 2011 - 1 - revision a10 table of contents- 1 ? general des cription ......................................................................................................... 4 ? 2 ? features ....................................................................................................................... .......... 5 ? 3 ? parts inform ation list ..................................................................................................... 6 ? 4 ? pin config urations............................................................................................................. 7 ? 5 ? pin descri ptions ............................................................................................................... ... 9 ? 6 ? block diagram .................................................................................................................. .. 11 ? 7 ? functional d escription.................................................................................................. 12 ? 7.1 ? on-chip fl ash eprom ................................................................................................ 12 ? 7.2 ? i/o ports...................................................................................................................... .. 12 ? 7.3 ? serial i/o ..................................................................................................................... .. 12 ? 7.4 ? timers ........................................................................................................................... 12 ? 7.5 ? interrupts..................................................................................................................... .. 12 ? 7.6 ? data po inters ................................................................................................................ 13 ? 7.7 ? architecture................................................................................................................... 13 ? 7.7.1 ? alu ............................................................................................................................ .... 13 ? 7.7.2 ? accumula tor ................................................................................................................... 13 ? 7.7.3 ? b regi ster..................................................................................................................... .. 13 ? 7.7.4 ? program stat us word ..................................................................................................... 13 ? 7.7.5 ? scratch-pa d ram ........................................................................................................... 13 ? 7.7.6 ? stack po inter .................................................................................................................. 13 ? 8 ? memory orga nization...................................................................................................... 14 ? 8.1 ? program memory (o n-chip flash) ................................................................................. 14 ? 8.2 ? scratch-pad ram and register map ............................................................................ 14 ? 8.2.1 ? working r egister s .......................................................................................................... 16 ? 8.2.2 ? bit addressabl e locat ions .............................................................................................. 17 ? 8.2.3 ? stack .......................................................................................................................... .... 17 ? 9 ? special function registers ......................................................................................... 18 ? 9.1 ? sfr detail bit descriptions .......................................................................................... 20 ? 10 ? instruction.................................................................................................................... ...... 35 ? 10.1 ? instruction timing.......................................................................................................... 43 ? 11 ? power mana gement.......................................................................................................... 44 ? 11.1 ? idle mode ...................................................................................................................... 44 ? 11.2 ? power down mode ....................................................................................................... 44 ? 12 ? reset cond itions............................................................................................................... 45 ? 12.1 ? sources of reset............................................................................................................ 45 ? 12.1.1 ? external reset .............................................................................................................. 45 ? 12.1.2 ? software reset ............................................................................................................. 45 ? 12.1.3 ? watchdog time r reset................................................................................................. 45 ?
w78e054d/w78e052d/w78e051d data sheet - 2 - 12.2 ? reset state ................................................................................................................... 45 ? 13 ? interrupts ..................................................................................................................... ...... 46 ? 13.1 ? interrupt sources .......................................................................................................... 46 ? 13.2 ? priority level structure ................................................................................................. 46 ? 13.3 ? interrupt response time .............................................................................................. 48 ? 13.4 ? interrupt inputs.............................................................................................................. 49 ? 14 ? programmable time rs/counters ............................................................................... 50 ? 14.1 ? timer/counter s 0 & 1.................................................................................................... 50 ? 14.2 ? time-base se lection..................................................................................................... 50 ? 14.2.1 ? mode 0 ......................................................................................................................... 50 ? 14.2.2 ? mode 1 ......................................................................................................................... 50 ? 14.2.3 ? mode 2 ......................................................................................................................... 51 ? 14.2.4 ? mode 3 ......................................................................................................................... 51 ? 14.3 ? timer/count er 2 ............................................................................................................ 52 ? 14.3.1 ? capture mode............................................................................................................... 52 ? 14.3.2 ? auto-reload mode, counti ng up .................................................................................. 53 ? 14.3.3 ? auto-reload mode, co unting up /down ......................................................................... 53 ? 14.3.4 ? baud rate gener ator mode ......................................................................................... 54 ? 15 ? watchdog timer................................................................................................................. 55 ? 16 ? serial port .................................................................................................................... ...... 57 ? 16.1 ? mode 0 ........................................................................................................................ 57 ? 16.2 ? mode 1 ........................................................................................................................ 58 ? 16.3 ? mode 2 ........................................................................................................................ 59 ? 17 ? flash rom code boot mode sl ection........................................................................ 62 ? 18 ? isp (in-system programming) ........................................................................................ 63 ? 19 ? config bits .................................................................................................................... ....... 67 ? 20 ? electrical cha racteristics......................................................................................... 69 ? 20.1 ? absolute maxi mum ratings .......................................................................................... 69 ? 20.2 ? dc electrical ch aracteristics ...................................................................... 70 ? 20.3 ? ac electrical ch aracteristics ...................................................................... 71 ? 20.3.1 ? clock input waveform .................................................................................................. 71 ? 20.3.2 ? program fetch cycle.................................................................................................... 72 ? 20.3.3 ? data read cycle .......................................................................................................... 72 ? 20.3.4 ? data writ e cycle........................................................................................................... 72 ? 20.3.5 ? port acce ss cycle ........................................................................................................ 73 ? 20.3.6 ? program o peratio n ....................................................................................................... 73 ? 20.4 ? timing wa veforms ....................................................................................................... 74 ? 20.4.1 ? program fetch cycle.................................................................................................... 74 ? 20.4.2 ? data read cycle .......................................................................................................... 74 ? 20.4.3 ? data writ e cycle........................................................................................................... 75 ? 20.4.4 ? port acce ss cycle ........................................................................................................ 75 ? 20.4.5 ? reset pin ac cess cycle ............................................................................................... 76 ? 21 ? application circuits ........................................................................................................ 77 ?
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 3 - revision a10 21.1 ? external program me mory and cr ystal ........................................................................ 77 ? 21.2 ? expanded external data me mory and o scillat or.......................................................... 77 ? 21.3 ? internal program memory and os cillator for e ft application ...................................... 78 ? 21.4 ? reference value of xtal ............................................................................................. 78 ? 22 ? applicatio n note ............................................................................................................... 79 ? 23 ? package dime nsio ns ......................................................................................................... 84 ? 23.1 ? 40-pin dip ..................................................................................................................... 84 ? 23.2 ? 44-pin plcc ................................................................................................................. 85 ? 23.3 ? 44-pin pqfp ................................................................................................................. 86 ? 23.4 ? 48-pin lqfp.................................................................................................................. 87 ? 24 ? revision histor y ............................................................................................................... . 88 ?
w78e054d/w78e052d/w78e051d data sheet - 4 - 1 general description the w78e054d/w78e052d/w78e051d series is an 8-bit microcontroller which can accommodate a wider frequency range with low power consumpt ion. the instruction set for the w78e054d/ w78e052d/ w78e051d series is fully compatible with the standard 8052. the w78e054d/w78e052d/w78e051d series contai ns 16k/8k/4k bytes flash eprom programma- ble by hardware writer; a 256 bytes ram; four 8-bit bi-directional (p0, p1, p2, p3) and bit-addressable i/o ports; an additional 4-bit i/o port p4; three 16- bit timer/counters; a hardware watchdog timer and a serial port. these peripherals are supported by 8 sources 4-level interrupt capability. to facilitate pro- gramming and verification, the flash eprom inside the w78e054d/w78e052d/w78e051d series allows the program memory to be programmed and r ead electronically. once the code is confirmed, the user can protect the code for security. the w78e054d/w78e052d/w78e051d series microcont roller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. the idle mode turns off the proc- essor clock but allows for continued peripheral opera tion. the power-down mode stops the crystal os- cillator for minimum power consumption. the exter nal clock can be stopped at any time and in any state without affecting the processor. the w 78e054d/w78e052d/w78e051d series contains in- system programmable (isp) 2kb ldrom for loader pr ogram, operating voltage from 3.3v to 5.5v. note: if the applied v dd is not stable, especially with long transition time of power on/off, it?s recommended to apply an external reset ic to the rst pin for improving the stability of sys- tem.
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 5 - revision a10 2 features ? fully static design 8-bit cmos microcontroller ? optional 12t or 6t mode ? 12t mode, 12 clocks per machine cycle operation (default), speed up to 40 mhz/5v ? 6t mode, 6 clocks per machine cycle operati on set by the writer, speed up to 20 mhz/5v ? wide supply voltage of 2.4v to 5.5v ? temperature grade is (-40 o c~85 o c) ? pin and instruction-sets compatible with mcs-51 ? 256 bytes of on-chip scratchpad ram ? 16k/8k/4k bytes electrically erasable/programmable flash eprom ? 2k bytes ldrom support isp function (reference application note) ? 64kb program memory address space ? 64kb data memory address space ? four 8-bit bi-directional ports ? 8-sources, 4-level interrupt capability ? one extra 4-bit bit-addressable i/o port, additional int2 / int3 (available on pqfp, plcc and lqfp package) ? three 16-bit timer/counters ? one full duplex serial port ? watchdog timer ? emi reduction mode ? software reset ? built-in power management with idle mode and power down mode ? code protection ? packages: dip40, plcc44, pqfp44, lqfp48
w78e054d/w78e052d/w78e051d data sheet - 6 - 3 parts information list part no. ram ldrom size aprom size package temperature grade 2k bytes 14k bytes w78e054ddg 0 16k bytes dip-40 pin -40 o c~85 o c 2k bytes 14k bytes w78e054dpg 0 16k bytes plcc-44 pin -40 o c~85 o c 2k bytes 14k bytes W78E054DFG 0 16k bytes pqfp-44 pin -40 o c~85 o c 2k bytes 14k bytes w78e054dlg 0 16k bytes lqfp-48 pin -40 o c~85 o c w78e052ddg dip-40 pin -40 o c~85 o c w78e052dpg plcc-44 pin -40 o c~85 o c w78e052dfg pqfp-44 pin -40 o c~85 o c w78e052dlg 2k bytes 8k bytes lqfp-48 pin -40 o c~85 o c w78e051ddg dip-40 pin -40 o c~85 o c w78e051dpg plcc-44 pin -40 o c~85 o c w78e051dfg pqfp-44 pin -40 o c~85 o c w78e051dlg 256 bytes 2k bytes 4k bytes lqfp-48 pin -40 o c~85 o c table 3?1: lad free (rohs) parts information list
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 7 - revision a10 4 pin configurations 18 6 5 4 3 2 1 44 43 42 41 40 19 20 21 22 23 24 25 26 27 28 p1.3 p1.2 p1.4 t2ex, p1.1 t2, p1.0 ad0, p0.0 int3, p4.2 ad1, p0.1 ad2, p0.2 ad3, p0.3 vdd xtal2 xtal1 vss p2.1, a9 p4.0 p2.2, a10 p2.3, a11 p2.4, a12 p2.0, a8 p3.7, rd p3.6, wr dip 40-pin
w78e054d/w78e052d/w78e051d data sheet - 8 - 8 12 37 7 10 9 11 44 43 42 41 40 39 38 36 35 34 32 33 30 31 28 29 26 27 24 25 23 13 14 15 16 17 18 19 20 21 22 p1.6 p1.5 rst p1.7 rxd, p3.0 txd, p3.1 t0, p3.4 t1, p3.5 p1.3 p1.2 p1.4 t2ex, p1.1 t2, p1.0 ad0, p0.0 ad1, p0.1 ad2, p0.2 ad3, p0.3 vdd ale p0.7, ad7 p4.1 p0.6, ad6 p0.5, ad5 p0.4, ad4 p2.5, a13 p2.6, a14 p2.7, a15 xtal2 xtal1 vss p2.1, a9 p4.0 p2.2, a10 p2.3, a11 p2.0, a8 pqfp 44-pin int0, p3.2 p3.7, rd int1, p3.3 psen ea p3.6, wr 2 1 4 3 5 6 int2, p4.3 int3, p4.2 2 44 1 4 3 6 5 8 7 10 9 11 48 42 41 40 39 38 37 32 33 30 31 28 29 26 27 25 13 14 15 16 18 19 20 21 22 p2.7, a15 psen ad0, p0.0 ale ea p4.1 p0.6, ad6 p0.5, ad5 p2.4, a12 p2.3, a11 p2.2, a10 p2.1, a9 xtal2 p3.7, rd p3.6, wr xtal1 int2, p4.3 int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 p1.6 p1.7 rst ad2, p0.3 ad2, p0.2 ad1, p0.1 p1.3 p1.4 p1.5 p1.2 p2.0, a8 p4.0 vss 12 17 23 24 34 35 36 46 47 43 45 p2.6, a14 p2.5, a13 nc vdd int3, p4.2 t2, p1.0 t2ex, p1.1 p0.7, ad7 p0.4, ad4 p3.1 p3.0 nc nc nc lqfp 48-pin p2.4, a12
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 9 - revision a10 5 pin descriptions symbol type descriptions ea i external access enable: this pin forces the processor to execute out o f external rom. it should be kept high to access internal rom. the rom address and data will not be present on the bus if e a pin is high and the program coun- ter is within internal rom area. ot herwise they will be present on the bus. psen o h program store enable: psen enables the external rom data onto the port 0 address/data bus during fetch and movc operations. when internal rom access is performed, no psen strobe signal outputs from this pin. ale o h address latch enable: ale is used to enable the address la tch that sepa- rates the address from the data on port 0. rst i l reset: a high on this pin for two machine cy cles while the oscillator is running resets the device. xtal1 i crystal1: this is the crystal oscillator input. this pin may be driven by an ex- ternal clock. xtal2 o crystal2: this is the crystal oscillator output. it is the inversion of xtal1. vss i ground: ground potential vdd i power supply: supply voltage for operation. p0.0 ? p0.7 i/o d port 0: port 0 is an open-drain bi-directional i/o port. this port also provides a multiplexed low order address/data bus during accesses to external memory. p1.0 ? p1.7 i/o h port 1: port 1 is a bi-directional i/o port with internal pull-ups. the bits have alternate functions which are described below: t2 (p1.0): timer/counter 2 external count input t2ex (p1.1): timer/counter 2 reload/capture control p2.0 ? p2.7 i/o h port 2: port 2 is a bi-directional i/o port with internal pull-ups. this port also provides the upper address bits for accesses to external memory.
w78e054d/w78e052d/w78e051d data sheet - 10 - pin description, continued symbol type descriptions p3.0 ? p3.7 i/o h port 3: port 3 is a bi-directional i/o port with internal pull-ups. all bits have al- ternate functions, which are described below: rxd (p3.0): serial port 0 input txd (p3.1): serial port 0 output int0 (p3.2) : external interrupt 0 int1 (p3.3) : external interrupt 1 t0 (p3.4) : timer 0 external input t1 (p3.5) : timer 1 external input wr (p3.6) : external data memory write strobe rd (p3.7) : external data memory read strobe p4.0 ? p4.3 i/o h port 4: another bit-addressable bidirectional i/o port p4. p4.3 and p4.2 are alternative function pins. it can be used as general i/o port or external interrupt input sources ( int2 / int3 ). * note: type i: input, o: output, i/o: bi-directional , h: pull-high, l: pull-low, d: open drain. in application if mcu pins need external pull- up, it is recommended to add a pull-up resistor (10k ) between pin and power (v dd ) instead of directly wiring pin to v dd for enhancing emc.
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 11 - revision a10 6 block diagram figure 6?1 w78e054d/w78e052d/w78e051d block diagram
w78e054d/w78e052d/w78e051d data sheet - 12 - 7 functional description the w78e054d/w78e052d/w78e051d series architec ture consists of a core controller surrounded by various registers, five general purpose i/o ports, 16k/8k/4k flash eprom, 2k flash eprom for isp function, 256 bytes of ram, th ree timer/counters, and a serial port. the processor supports 111 different op-codes and references both a 64k prog ram address space and a 64k data storage space. 7.1 on-chip flash eprom the w78e054d/w78e052d/w78e051d series include one 16k/8k/4k bytes of main flash eprom for application program. 7.2 i/o ports the w78e054d/w78e052d/w78e051d series has four 8-bit ports and one extra 4-bit port. port 0 can be used as an address/data bus when external prog ram is running or external memory/device is ac- cessed by movc or movx instruction. in these ca ses, it has strong pull-ups and pull-downs, and does not need any external pull-ups. otherwise it can be used as a general i/o port with open-drain circuit. port 2 is used chiefly as the upper 8-bits of the address bus when port 0 is used as an ad- dress/data bus. it also has strong pull-ups and pu ll-downs when it serves as an address bus. port1 and 3 act as i/o ports with alternate functions. port 4 is only available on plcc/pqfp/lqfp package type. it serves as a general purpose i/o port as port 1 and port 3. another bit-addressable bidirec- tional i/o port p4. p4.3 and p4.2 are alternative function pins. it can be used as general i/o port or external interrupt input sources ( int2 / int3 ). 7.3 serial i/o the w78e054d/w78e052d/w78e051d series have one seri al port that is functionally similar to the serial port of the original 8032 family. howeve r the serial port on t he w78e054d/ w78e052d/ w78e051d series can operate in different modes in order to obtain timing similarity as well. 7.4 timers timers 0, 1, and 2 each consist of two 8-bit data registers. these are called tl0 and th0 for timer 0, tl1 and th1 for timer 1, and tl2 and th2 for timer 2. the tcon and tmod registers provide con- trol functions for timers 0 and 1. the t2con regist er provides control functions for timer 2. rcap2h and rcap2l are used as reload/capture registers for timer 2. the operations of timer 0 and timer 1 are the same as in the 8051 cpu. timer 2 is a special feature of the w78e054d/w78e052d/w78e051d: it is a 16-bit timer/counter that is configured and controlled by the t2con register. like timers 0 and 1, timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit c/t2 in t2con. timer 2 has three operating modes: capture, auto-reload, and baud rate generato r. the clock speed at capture or auto-reload mode is the same as that of timers 0 and 1. 7.5 interrupts the interrupt structure in the w 78e054d/w78e052d/w78e051d is slight ly different from that of the standard 8052. due to the presence of additional features and peripherals, the number of interrupt sources and vectors has been increased. the w 78e054d/w78e052d/w78e051d provides 8 interrupt resources with four priority level, including four exte rnal interrupt sources, thre e timer interrupts, serial i/o interrupts.
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 13 - revision a10 7.6 data pointers the data pointer of w78e054d/w78e052d/w78e051d series is same as standard 8052 that have one 16-bit data pointer (dptr). 7.7 architecture the w78e054d/w78e052d/w78e051d series are bas ed on the standard 8052 device. it is built around an 8-bit alu that uses internal registers for temporary storage and control of the peripheral devices. it can execute the standard 8052 instruction set. 7.7.1 alu the alu is the heart of the w78e054d/w78e052d/w 78e051d series. it is responsible for the arith- metic and logical functions. it is also used in decision making, in case of jump instructions, and is also used in calculating jump addresses. the user cannot directly use the alu, but the instruction decoder reads the op-code, decodes it, and sequences the da ta through the alu and its associated registers to generate the required result. the alu mainly uses the acc which is a special function register (sfr) on the chip. another sfr, namely b register is also used multiply and divide instructions. the alu generates several status signals which are stor ed in the program status word register (psw). 7.7.2 accumulator the accumulator (acc) is the primary register used in arithmetic, logical and data transfer operations in the w78e054d/w78e052d/w78e051d series. since t he accumulator is directly accessible by the cpu, most of the high speed instructi ons make use of the acc as one argument. 7.7.3 b register this is an 8-bit register that is used as the se cond argument in the mul and div instructions. for all other instructions it can be used simply as a general purpose register. 7.7.4 program status word this is an 8-bit sfr that is used to store the status bits of the alu. it holds the carry flag, the auxiliary carry flag, general purpose flags, the register bank select, the overflow flag, and the parity flag. 7.7.5 scratch-pad ram the w78e054d/w78e052d/w78e051d series has a 256 byte on-chip scratch-pad ram. this can be used by the user for temporary storage during program execution. a certain sect ion of this ram is bit addressable, and can be directly addressed for this purpose. 7.7.6 stack pointer the w78e054d/w78e052d/w78e051d series has an 8- bit stack pointer which points to the top of the stack. this stack resides in the scratc h pad ram in the w78e054d/w78e052d/w78e051d. hence the size of the stack is lim ited by the size of this ram.
w78e054d/w78e052d/w78e051d data sheet - 14 - 8 memory organization the w78e054d/w78e052d/w78e051d series separate the memory into two separate sections, the program memory and the data memory. the program memory is used to store the instruction op- codes, while the data memory is used to store data or for memory mapped devices. indirect addressing ram direct & indirect addressing ram sfrs direct addressing only 00h 7fh 80h ffh 64k bytes external data memory 14k/8k/4kb aprom ffffh 0000h 3fffh 3800h 2kb ldrom 0000h 16kb aprom 3fffh 0000h or figure 8?1 memory map 8.1 program memory (on-chip flash) the program memory on the w78e054d/w78e052 d/w78e051d series can be up to 16k/8k/4k bytes (2k bytes for isp f/w, share with the w78e05 4d) long. all instructions are fetched for execution from this memory area. the movc instructi on can also access this memory region. 8.2 scratch-pad ram and register map as mentioned before the w78e054 d/w78e052d/w78e051d series have separate program and data memory areas. there are also several special function registers (sfrs) which can be accessed by software. the sfrs can be accessed only by dire ct addressing, while the on-chip ram can be ac- cessed by either direct or indirect addressing.
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 15 - revision a10 indirect ram addressing direct & indirect ram addressing sfr direct addressing only 00h 7fh 80h ffh 256 bytes ram and sfr data memory space figure 8?2 w78e054d/w78e052d/w78e 051d ram and sfr memory map since the scratch-pad ram is only 256bytes it can be used only when data cont ents are small. there are several other special purpose areas within the scratch-pad ram. these are illustrated in next fig- ure.
w78e054d/w78e052d/w78e051d data sheet - 16 - bank 0 bank 1 bank 2 bank 3 03 02 01 00 04 05 06 07 0b 0a 09 08 0c 0d 0e 0f 13 12 11 10 14 15 16 17 1b 1a 19 18 1c 1d 1e 1f 23 22 21 20 24 25 26 27 2b 2a 29 28 2c 2d 2e 2f 33 32 31 30 34 35 36 37 3b 3a 39 38 3c 3d 3e 3f 43 42 41 40 44 45 46 47 4b 4a 49 48 4c 4d 4e 4f 53 52 51 50 54 55 56 57 5b 5a 59 58 5c 5d 5e 5f 63 62 61 60 64 65 66 67 6b 6a 69 68 6c 6d 6e 6f 73 72 71 70 74 75 76 77 7b 7a 79 78 7c 7d 7e 7f direct ram indirect ram 00h 07h 28h 08h 0fh 10h 17h 18h 1fh 20h 21h 22h 23h 24h 25h 26h 27h 29h 2ah 2bh 2ch 2dh 2eh 2fh 30h 7fh 80h ffh figure 8?3 scratch-pad ram 8.2.1 working registers there are four sets of working r egisters, each consisting of eight 8-bit registers. these are termed as banks 0, 1, 2, and 3. individual re gisters within these banks can be di rectly accessed by separate in- structions. these individual registers are named as r0, r1, r2, r3, r4, r5, r6 and r7. however, at one time the w78e054d/w78e052d/w78e051d series can work with only one particular bank. the bank selection is done by setting rs1-rs0 bits in the psw. the r0 and r1 registers are used to store the address for indi rect accessing.
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 17 - revision a10 8.2.2 bit addressable locations the scratch-pad ram area from location 20h to 2fh is byte as well as bit addressable. this means that a bit in this area can be individually addressed. in addition some of the sfrs are also bit ad- dressable. the instruction decoder is able to distingu ish a bit access from a byte access by the type of the instruction itself. in the sfr area, any existing sfr whose address ends in a 0 or 8 is bit address- able. 8.2.3 stack the scratch-pad ram can be used for the stack. this area is selected by the stack pointer (sp), which stores the address of the t op of the stack. whenever a jump, ca ll or interrupt is invoked the re- turn address is placed on the stack. there is no rest riction as to where the stack can begin in the ram. by default however, the stack pointer contains 07h at reset. the user can then change this to any value desired. the sp will point to the last us ed value. therefore, the sp will be incremented and then address saved onto the stack. conversely, while popping from the stack the contents will be read first, and then the sp is decreased.
w78e054d/w78e052d/w78e051d data sheet - 18 - 9 special function registers the w78e054d/w78e052d/w78e051d series uses special function registers (sfrs) to control and monitor peripherals and their modes. the sfrs reside in the register locations 80-ffh and are ac- cessed by direct addressing only. some of the sfrs ar e bit addressable. this is very useful in cases where users wish to modify a particular bit wit hout changing the others. t he sfrs that are bit ad- dressable are those whose addresses end in 0 or 8. the w78e054d/w78e052d/w78e051d series contain all the sfrs present in the standard 8052. however some additional sfrs are added. in some cases the unused bits in the original 8052, have been given new functions. the list of the sfrs is as follows. f8 ff f0 b f7 e8 ef e0 acc e7 d8 p4 df d0 psw d7 c8 t2con t2mod rcap2l rcap2h tl2 th2 cf c0 xicon sfral sfrah sfrrd sfrcn c7 b8 ip eapage chpcon bf b0 p3 iph b7 a8 ie af a0 p2 a7 98 scon sbuf 9f 90 p1 97 88 tcon tmod tl0 tl1 th0 th1 auxr wdtc 8f 80 p0 sp dpl dph p0upr pcon 87 table 9?1: special function register location table note: 1. the sfrs in the column with dark borders are bit-addressable 2. the table is condensed with eight locations per row. empty locations indicate that these are no reg- isters at these addresses. when a bit or register is not implemented, it will read high.
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 19 - revision a10 special function registers: symbol definition address msb bit address, symbol lsb reset b b register f0h (f7) (f6) (f5) (f4) (f3) (f2) (f1) (f0) 0000 0000b acc accumulator e0h (e7) (e6) (e5) (e4) (e3) (e2) (e1) (e0) 0000 0000b p4 port 4 d8h int2 int3 0000 1111b psw program status word d0h (d7) cy (d6) ac (d5) f0 (d4) rs1 (d3) rs0 (d2) ov (d1) f1 (d0) p 0000 0000b th2 t2 reg. high cdh 0000 0000b tl2 t2 reg. low cch 0000 0000b rcap2h t2 capture low cbh 0000 0000b rcap2l t2 capture high cah 0000 0000b t2mod timer 2 mode c9 dcen 0000 0000b t2con timer 2 control c8h (cf) tf2 (ce) exf2 (cd) rclk (cc) tclk (cb) exen2 (ca) tr2 (c9) c/t2 (c8) cp/rl2 0000 0000b sfrcn sfr program of control c7h noe nce ctrl3 ctrl2 ctrl1 ctrl0 0000 0000b sfrrd sfr program of data register c6h 0000 0000b sfrah sfr program of address high byte c5h 0000 0000b sfral sfr program of address low byte c4h 0000 0000b xicon external interrupt control c0h px3 ex3 ie3 it3 px2 ex2 ie2 it2 0000 0000b chpcon chip control bfh swrst - - - - fboots l enp 0000 0000b eapage erase page operation modes beh eapg1 eapg0 0000 0000b ip interrupt priority b8h (bf) - (be) - (bd) pt2 (bc) ps (bb) pt1 (ba) px1 (b9) pt0 (b8) px0 1100 0000b iph interrupt priority high b7h 0000 0000b p3 port 3 b0h (b7) rd (b6) wr (b5) t1 (b4) t0 (b3) int1 (b2) int0 (b1) txd (b0) rxd 1111 1111b ie interrupt enable a8h (af) ea (ae) - (ad) et2 (ac) es (ab) et1 (aa) ex1 (a9) et0 (a8) ex0 0100 0000b p2 port 2 a0h (a7) a15 (a6) a14 (a5) a13 (a4) a12 (a3) a11 (a2) a10 (a1) a9 (a0) a8 1111 1111b sbuf serial buffer 99h 0000 0000b scon serial control 98h (9f) sm0/fe (9e) sm1 (9d) sm2 (9c) ren (9b) tb8 (9a) rb8 (99) ti (98) ri 0000 0000b p1 port 1 90h (97) (96) (95) (94) (93) (92) (91) t2ex (90) t2 1111 1111b wdtc watchdog control 8fh enw clrw widl - - ps2 ps1 ps0 0000 0000b auxr auxiliary 8eh - - - - aleoff 0000 0110b th1 timer high 1 8dh 0000 0000b th0 timer high 0 8ch 0000 0000b tl1 timer low 1 8bh 0000 0000b tl0 timer low 0 8ah 0000 0000b tmod timer mode 89h gate c/t m1 m0 gate c/t m1 m0 0000 0000b tcon timer control 88h (8f) tf1 (8e) tr1 (8d) tf0 (8c) tr0 (8b) ie1 (8a) it1 (89) ie0 (88) it0 0000 0000b pcon power control 87h smod smod0 - por gf1 gf0 pd idl 0011 0000b p0upr port 0 pull up option register 86h - - - - - - - p0up 0000 0001b dph data pointer high 83h 0000 0000b
w78e054d/w78e052d/w78e051d data sheet - 20 - dpl data pointer low 82h 0000 0000b sp stack pointer 81h 0000 0111b p0 port 0 80h (87) (86) (85) (84) (83) (82) (81) (80) 1111 1111b 9.1 sfr detail bit descriptions port 0 bit: 7 6 5 4 3 2 1 0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 mnemonic: p0 address: 80h bit name function 7-0 p0.[7:0] port 0 is an open-drain bi-directional i/o port if sfr p0upr. 0 (bit p0up) clear to ?0?, and when sfr p0upr.0 (bit p0up) set to ?1?, port 0 pins are internally pulled-up. this port also provides a multiplexed low order address/data bus during accesses to external memory. stack pointer bit: 7 6 5 4 3 2 1 0 sp.7 sp.6 sp.5 sp.4 sp.3 sp.2 sp.1 sp.0 mnemonic: sp address: 81h bit name function 7-0 sp.[7:0] the stack pointer stores the scratc h-pad ram address where the stack begins. in other words it always points to the top of the stack. data pointer low bit: 7 6 5 4 3 2 1 0 dpl.7 dpl.6 dpl.5 dpl.4 dpl.3 dpl.2 dpl.1 dpl.0 mnemonic: dpl address: 82h bit name function 7-0 dpl.[7:0] this is the low byte of the standard 8052 16-bit data pointer. data pointer high bit: 7 6 5 4 3 2 1 0 dph.7 dph.6 dph.5 dph.4 dph.3 dph.2 dph.1 dph.0 mnemonic: dph address: 83h bit name function 7-0 dph.[7:0] this is the high byte of the standard 8052 16-bit data pointer. port 0 pull up option register bit: 7 6 5 4 3 2 1 0
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 21 - revision a10 - - - - - - - p0up mnemonic: p0upr address: 86h bit name function 0 p0up 0: port 0 pins are open-drain. 1: port 0 pins are internally pulled-up. port 0 is structurally the same as port 2. power control bit: 7 6 5 4 3 2 1 0 smod smod0 - por gf1 gf0 pd idl mnemonic: pcon address: 87h bit name function 7 smod 1: this bit doubles the serial port baud rate in mode 1, 2, and 3 when set to 1. 6 smod 0 0: framing error detection disable. scon .7 (sm0/fe) bit is used as sm0 (stan- dard 8052 function). 1: framing error detection enable. scon.7 (sm0/fe) bit is used to reflect as frame error (fe) status flag. 5 - reserved 4 por 0: cleared by software. 1: set automatically when a power-on reset has occurred. 3 gf1 general purpose user flags. 2 gf0 general purpose user flags. 1 pd 1: the cpu goes into the power down mode. in this mode, all the clocks are stopped and program execution is frozen. 0 idl 1: the cpu goes into the idle mode. in this mode, the clocks cpu clock stopped, so program execution is frozen. but the clock to the serial, timer and interrupt blocks is not stopped, and these blocks continue operating. timer control bit: 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 mnemonic: tcon address: 88h bit name function 7 tf1 timer 1 overflow flag. this bit is se t when timer 1 overflows. it is cleared auto- matically when the program does a timer 1 interrupt service routine. software can also set or clear this bit. 6 tr1 timer 1 run control. this bit is set or cleared by software to turn timer/counter on or off. 5 tf0 timer 0 overflow flag. this bit is se t when timer 0 overflows. it is cleared auto- matically when the program does a timer 0 interrupt service routine. software can also set or clear this bit.
w78e054d/w78e052d/w78e051d data sheet - 22 - 4 tr0 timer 0 run control. this bit is set or cleared by software to turn timer/counter on or off. 3 ie1 interrupt 1 edge detect flag: set by hardware when an edge/level is detected on 1int . this bit is cleared by hardware when t he service routine is vectored to only if the interrupt was edge triggered. otherwise it follows the inverse of the pin. 2 it1 interrupt 1 type control. set/cleared by software to specify falling edge/ low level triggered external inputs. 1 ie0 interrupt 0 edge detect flag. set by hardware when an edge/level is detected on 0int . this bit is cleared by hardware wh en the service routine is vectored to only if the interrupt was edge triggered. other wise it follows the inverse of the pin. 0 it0 interrupt 0 type control: set/cleared by software to specify falling edge/ low level triggered external inputs. timer mode control bit: 7 6 5 4 3 2 1 0 gate tc / m1 m0 gate tc / m1 m0 timer1 timer0 mnemonic: tmod address: 89h bit name function 7 gate gating control: when this bit is set, timer/counter 1 is enabled only while the 1int pin is high and the tr1 control bit is set. when cleared, the 1int pin has no effect, and timer 1 is enabled whenever tr1 control bit is set. 6 tc/ timer or counter select: when clear, timer 1 is incremented by the internal clock. when set, the timer counts falling edges on the t1 pin. 5 m1 timer 1 mode select bit 1. see table below. 4 m0 timer 1 mode select bit 0. see table below. 3 gate gating control: when this bit is set, timer/counter 0 is enabled only while the 0int pin is high and the tr0 control bit is set. when cleared, the 0int pin has no ef- fect, and timer 0 is enabled whenever tr0 control bit is set. 2 tc/ timer or counter select: when clear, timer 0 is incremented by the internal clock. when set, the timer counts falling edges on the t0 pin. 1 m1 timer 0 mode select bit 1. see table below. 0 m0 timer 0 mode select bit 0. see table below. m1, m0: mode select bits: m1 m0 mode 0 0 mode 0: 13-bit timer/counter tlx serves as 5-bit pre-scale. 0 1 mode 1: 16-bit timer/counter, no pre-scale. 1 0 mode 2: 8-bit timer/counter with auto-reload from thx. 1 1 mode 3: (timer 0) tl0 is an 8-bit timer/ counter controlled by the standard timer0 control bits. th0 is an 8-bit timer only controlled by timer1 control bits. (timer 1)
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 23 - revision a10 timer/counter 1 is stopped. timer 0 lsb bit: 7 6 5 4 3 2 1 0 tl0.7 tl0.6 tl0.5 tl0.4 tl0.3 tl0.2 tl0.1 tl0.0 mnemonic: tl0 address: 8ah bit name function 7-0 tl0.[7:0] timer 0 lsb. timer 1 lsb bit: 7 6 5 4 3 2 1 0 tl1.7 tl1.6 tl1.5 tl1.4 tl1.3 tl1.2 tl1.1 tl1.0 mnemonic: tl1 address: 8bh bit name function 7-0 tl1.[7:0] timer 1 lsb. timer 0 msb bit: 7 6 5 4 3 2 1 0 th0.7 th0.6 th0.5 th0.4 th0.3 th0.2 th0.1 th0.0 mnemonic: th0 address: 8ch bit name function 7-0 th0.[7:0] timer 0 msb. timer 1 msb bit: 7 6 5 4 3 2 1 0 th1.7 th1.6 th1.5 th1.4 th1.3 th1.2 th1.1 th1.0 mnemonic: th1 address: 8dh bit name function 7-0 th1.[7:0] timer 1 msb. auxr bit: 7 6 5 4 3 2 1 0 - - - - - - - ale_off mnemonic: auxr address: 8eh
w78e054d/w78e052d/w78e051d data sheet - 24 - bit name function 0 ale_off 1: disenable ale output 0: enable ale output watchdog timer control register bit: 7 6 5 4 3 2 1 0 enw clrw widl - - ps2 ps1 ps0 mnemonic: wdtc address: 8fh bit name function 7 enw enable watch-dog if set. 6 clrw clear watch-dog timer and pre-scalar if set. this flag will be cleared automati- cally. 5 widl if this bit is set, watch-dog is enabled under idle mode. if cleared, watch-dog is disabled under idle mode. default is cleared. 2-0 ps2-0 watch-dog pre-scalar timer select. pre-scalar is selected when set ps2 ? 0 as fol- lows: ps2 ps1 ps0 pre-scalar select 0 0 0 2 0 0 1 8 0 1 0 4 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256 port 1 bit: 7 6 5 4 3 2 1 0 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 mnemonic: p1 address: 90h bit name function 7-0 p1.[7:0] general purpose i/o port. most instructions will read the port pins in case of a port read access, however in case of read-modi fy-write instructions, the port latch is read. serial port control bit: 7 6 5 4 3 2 1 0 sm0/fe sm1 sm2 ren tb8 rb8 ti ri
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 25 - revision a10 mnemonic: scon address: 98h bit name function 7 sm0/fe serial port mode select bit 0 or framing error flag: the smod0 bit in pcon sfr determines whether this bit acts as sm0 or as fe. the operation of sm0 is described below. when used as fe, this bi t will be set to indicate an invalid stop bit. this bit must be manually cleared in software to clear the fe condition. 6 sm1 serial port mode select bit 1. see table below. 5 sm2 multiple processors communication. setting this bit to 1 enables the multiproces- sor communication feature in mode 2 and 3. in mode 2 or 3, if sm2 is set to 1, then ri will not be activated if the received 9th data bit (rb8) is 0. in mode 1, if sm2 = 1, then ri will not be activated if a valid stop bit was not received. in mode 0, the sm2 bit controls the serial por t clock. if set to 0, then the serial port runs at a divide by 12 clock of the osc illator. this gives compatibility with the standard 8052. when set to 1, the serial clock become divide by 4 of the oscilla- tor clock. this results in faster synchronous serial communication. 4 ren receive enable: 0: disable serial reception. 1: enable serial reception. 3 tb8 this is the 9th bit to be transmitted in modes 2 and 3. this bit is set and cleared by software as desired. 2 rb8 in modes 2 and 3 this is the received 9th data bit. in mode 1, if sm2 = 0, rb8 is the stop bit that was received. in mode 0 it has no function. 1 ti transmit interrupt flag: this flag is se t by hardware at the end of the 8th bit time in mode 0, or at the beginning of the st op bit in all other modes during serial transmission. this bit must be cleared by software. 0 ri receive interrupt flag: this flag is set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bits time in the other modes during serial reception. however the restrictions of sm2 apply to this bit. this bit can be cleared only by software. sm1, sm0: mode select bits: mode sm0 sm1 description length baud rate 0 0 0 synchronous 8 tclk divided by 4 or 12 1 0 1 asynchronous 10 variable 2 1 0 asynchronous 11 tclk divided by 32 or 64 3 1 1 asynchronous 11 variable serial data buffer bit: 7 6 5 4 3 2 1 0 sbuf.7 sbuf.6 sbuf.5 sbuf.4 sbuf.3 sbuf.2 sbuf.1 sbuf.0 mnemonic: sbuf address: 99h
w78e054d/w78e052d/w78e051d data sheet - 26 - bit name function 7~0 sbuf serial data on the serial port is read from or written to this location. it actually consists of two separate internal 8-bit re gisters. one is the receive resister, and the other is the transmit buffer. any read access gets data from the receive data buffer, while write access is to the transmit data buffer. port 2 bit: 7 6 5 4 3 2 1 0 p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 mnemonic: p2 address: a0h bit name function 7-0 p2.[7:0] port 2 is a bi-directional i/o port with inte rnal pull-ups. this port also provides the upper address bits for accesses to external memory. interrupt enable bit: 7 6 5 4 3 2 1 0 ea - et2 es et1 ex1 et0 ex0 mnemonic: ie address: a8h bit name function 7 ea global enable. enable/disable all interrupts. 6 - reserved 5 et2 enable timer 2 interrupt. 4 es enable serial port 0 interrupt. 3 et1 enable timer 1 interrupt. 2 ex1 enable external interrupt 1. 1 et0 enable timer 0 interrupt. 0 ex0 enable external interrupt 0. port 3 bit: 7 6 5 4 3 2 1 0 p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 mnemonic: p3 address: b0h p3.7-0: general purpose input/output port. mo st instructions will read the port pins in case of a port read access, however in case of read-modify-write instructions, t he port latch is read. these alter- nate functions are described below: bit name function 7 p3.7 rd
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 27 - revision a10 6 p3.6 wr 5 p3.5 t1 4 p3.4 t0 3 p3.3 int1 2 p3.2 int0 1 p3.1 tx 0 p3.0 rx interrupt high priority bit: 7 6 5 4 3 2 1 0 iph.7 iph.6 iph.5 iph.4 iph.3 iph.2 iph.1 iph.0 mnemonic: iph address: b7h bit name function 7 iph.7 1: interrupt high priority of int3 is highest priority level. 6 iph.6 1: interrupt high priority of int2 is highest priority level. 5 iph.5 1: interrupt high priority of timer 2 is highest priority level. 4 iph.4 1: interrupt high priority of serial port 0 is highest priority level. 3 iph.3 1: interrupt high priority of timer 1 is highest priority level. 2 iph.2 1: interrupt high priority of external interrupt 1 is highest priority level. 1 iph.1 1: interrupt high priority of timer 0 is highest priority level. 0 iph.0 1: interrupt high priority of external interrupt 0 is highest priority level. interrupt priority bit: 7 6 5 4 3 2 1 0 - - pt2 ps pt1 px1 pt0 px0 mnemonic: ip address: b8h bit name function 5 pt2 1: interrupt priority of timer 2 is higher priority level. 4 ps 1: interrupt priority of serial port 0 is higher priority level. 3 pt1 1: interrupt priority of timer 1 is higher priority level. 2 px1 1: interrupt priority of external interrupt 1 is higher priority level. 1 pt0 1: interrupt priority of timer 0 is higher priority level. 0 px0 1: interrupt priority of external interrupt 0 is higher priority level.
w78e054d/w78e052d/w78e051d data sheet - 28 - eapage erase page operation modes bit: 7 6 5 4 3 2 1 0 - - - - - - eapg1 eapg0 mnemonic: eapage address: bd bit name function 1 eapg1 1: to ease page1 when ease command is set. (ldrom) 0 eapg0 1: to ease page0 when ease command is set. (aprom) ;cpu clock = 12mhz/12t mode read_time equ 1 program_time equ 50 erase_time equ 5000 erase_aprom: mov eapage,#01h ;set eapage is aprom mov sfrcn,#erase_rom mov tl0,#low (65536-erase_time) mov th0,#high(65536-erase_time) setb tr0 mov chpcon,#00000011b mov eapage,#00h ;clear eapage clr tf0 clr tr0 ret erase_ldrom: mov eapage,#02h ;set eapage is ldrom mov sfrcn,#erase_rom mov tl0,#low (65536-erase_time) mov th0,#high(65536-erase_time) setb tr0 mov chpcon,#00000011b mov eapage,#00h ;clear eapage clr tf0 clr tr0 ret chip control bit: 7 6 5 4 3 2 1 0 swrst - - - - - isp enp mnemonic: chpcon address: bfh bit name function
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 29 - revision a10 7 swrst when this bit is set to 1 and enp is set to 1. it will enforce microcontroller reset to initial condition just like power on reset. this action will re-boot the microcontroller and start to normal operation. 1 isp the isp function select. when this bit is set to 1 and enp is set to 1. it will run isp function. 0 enp when this bit is set to 1 and swrst is set to 1. it will enforce microcontrol- ler reset to initial condition just like power on reset. when this bit is set to 1 and isp is set to 1. it will run isp function note1: chpcon = 0x81, it is software reset note2: chpcon = 0x03, isp function is enabled. external interrupt control bit: 7 6 5 4 3 2 1 0 px3 ex3 ie3 it3 px2 ex2 ie2 it2 mnemonic: xicon address: c0h bit name function 7 px3 external interrupt 3 priority is higher if set this bit to 1 6 ex3 enable external interrupt 3 if set this bit to 1 5 ie3 if it3 = 1, ie3 is set/cleared automa tically by hardware when interrupt is de- tected/serviced 4 it3 external interrupt 3 is falling-edge/low- level triggered when this bit is set/cleared by software 3 px2 external interrupt 2 priority is higher if set this to 1 2 ex2 enable external interrupt 2 if set this bit to 1 1 ie2 if it2 = 1, ie2 is set/cleared automa tically by hardware when interrupt is de- tected/serviced 0 it2 external interrupt 2 is falling-edge/low- level triggered when this bit is set/cleared by software sfr program of address low bit: 7 6 5 4 3 2 1 0 sfral.7 sfral.6 sfral.5 sfral.4 sfral.3 sfral.2 sfral.1 sfral.0 mnemonic: sfral address: c4h bit name function 7-0 sfral.[7:0] the programming address of on-chip flash memory in programming mode. sfrfal contains the low- order byte of address. sfr program of address high bit: 7 6 5 4 3 2 1 0
w78e054d/w78e052d/w78e051d data sheet - 30 - sfrah.7 sfrah.6 sfra h.5 sfrah.4 sfrah.3 sf rah.2 sfrah.1 sfrah.0 mnemonic: sfrah address: c5h bit name function 7-0 sfrah.[7:0] the programming address of on-chip flash memory in programming mode. sfrfah contains the high-order byte of address. sfr program for data bit: 7 6 5 4 3 2 1 0 sfrfd.7 sfrfd.6 sfrf d.5 sfrfd.4 sfrf d.3 sfrfd.2 sf rfd.1 sfrfd.0 mnemonic: sfrfd address: c6h bit name function 7-0 sfrfd.[7:0] the programming data for on- chip flash memory in programming mode. sfr for program control bit: 7 6 5 4 3 2 1 0 - oen cen ctrl3 ctrl2 ctrl1 ctrl0 mnemonic: sfrcn address: c7h bit name function 5 oen flash eprom output enable. 4 cen flash eprom chip enable. 3-0 ctrl[3:0] ctrl[3:0]: the flash control signals mode oen cen ctrl<3:0> sfrah, sfral sfrfd flash standby 1 1 x x x read company id 0 0 1011 0ffh, 0ffh data out read device id high 0 0 1100 0ffh, 0ffh data out read device id low 1 0 1100 0ffh, 0feh data out erase aprom 1 0 0010 x x erase verify aprom 0 0 1001 address in data out program aprom 1 0 0001 address in data in program verify aprom 0 0 1010 address in data out read aprom 0 0 0000 address in data out timer 2 control bit: 7 6 5 4 3 2 1 0 tf2 exf2 rclk tclk exen2 tr2 ct /2 cp rl /2
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 31 - revision a10 mnemonic: t2con address: c8h bit name function 7 tf2 timer 2 overflow flag: this bit is set when timer 2 overflows. it is also set when the count is equal to the capture register in down count mode. it can be set only if rclk and tclk are both 0. it is cleared only by software. software can also set or clear this bit. 6 exf2 timer 2 external flag: a negative transition on the t2ex pin (p1.1) or timer 2 overflow will cause this flag to set based on the cp rl /2 , exen2 and dcen bits. if set by a negative transition, this flag must be cleared by software. set- ting this bit in software or detection of a negative transition on t2ex pin will force a timer interrupt if enabled. 5 rclk receive clock flag: this bit determi nes the serial port 0 time-base when re- ceiving data in serial modes 1 or 3. if it is 0, then timer 1 overflow is used for baud rate generation, otherwise timer 2 over flow is used. setting this bit forces timer 2 in baud rate generator mode. 4 tclk transmit clock flag: this bit det ermines the serial port 0 time-base when transmitting data in modes 1 and 3. if it is set to 0, the timer 1 overflow is used to generate the baud rate clock otherwise timer 2 overflow is used. setting this bit forces timer 2 in baud rate generator mode. 3 exen2 timer 2 external enable. this bit enables the ca pture/reload function on the t2ex pin if timer 2 is not generating baud clocks for the serial port. if this bit is 0, then the t2ex pin will be ignor ed, otherwise a negative transition de- tected on the t2ex pin will result in capture or reload. 2 tr2 timer 2 run control. this bit enables/disables the operation of timer 2. clear- ing this bit will halt the timer 2 and preserve the current count in th2, tl2. 1 ct /2 counter/timer select. this bit determi nes whether timer 2 will function as a timer or a counter. independent of this bi t, the timer will run at 2 clocks per tick when used in baud rate generator mode. 0 cp rl /2 capture/reload select. this bit deter mines whether the capture or reload function will be used for timer 2. if either rclk or tclk is set, this bit will be ignored and the timer will function in an auto-reload mode following each over- flow. if the bit is 0 then auto-reload will occur when timer 2 overflows or a fal- ling edge is detected on t2ex pin if exen2 = 1. if this bit is 1, then timer 2 captures will occur when a falling edge is detected on t2ex pin if exen2 = 1. timer 2 mode control bit: 7 6 5 4 3 2 1 0 - - - - - - dcen mnemonic: t2mod address: c9h bit name function 0 dcen down count enable: this bit, in conj unction with the t2ex pin, controls the direction that timer 2 counts in 16-bit auto-reload mode.
w78e054d/w78e052d/w78e051d data sheet - 32 - timer 2 capture lsb bit: 7 6 5 4 3 2 1 0 rcap2l.7 rcap2l.6 rcap2l.5 rcap2l.4 rcap2l.3 rcap2l.2 rcap2l.1 rcap2l.0 mnemonic: rcap2l address: cah bit name function 7-0 rcap2l.[7:0] this register is used to capture the tl2 value when a timer 2 is configured in capture mode. rcap2l is also used as the lsb of a 16-bit reload value when timer 2 is configured in auto-reload mode. timer 2 capture msb bit: 7 6 5 4 3 2 1 0 rcap2h.7 rcap2h.6 rcap2h.5 rcap2h.4 rcap2h.3 rcap2h.2 rcap2h.1 rcap2h.0 mnemonic: rcap2h address: cbh bit name function 7-0 rcap2h.[7:0] this register is used to capture the th2 value when a timer 2 is configured in capture mode. rcap2h is also used as the msb of a 16-bit reload value when timer 2 is configured in auto-reload mode. timer 2 lsb bit: 7 6 5 4 3 2 1 0 tl2.7 tl2.6 tl2.5 tl2.4 tl2.3 tl2.2 tl2.1 tl2.0 mnemonic: tl2 address: cch bit name function 7-0 tl2.[7:0] timer 2 lsb timer 2 msb bit: 7 6 5 4 3 2 1 0 th2.7 th2.6 th2.5 th2.4 th2.3 th2.2 th2.1 th2.0 mnemonic: th2 address: cdh bit name function 7-0 th2.[7:0] timer 2 msb program status word bit: 7 6 5 4 3 2 1 0 cy ac f0 rs1 rs0 ov f1 p mnemonic: psw address: d0h
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 33 - revision a10 bit name function 7 cy carry flag: set for an arithmetic operation which re sults in a carry being generated from the alu. it is also used as the accumulator for the bit operations. 6 ac auxiliary carry: set when the previous operation resulted in a carry from the high order nibble. 5 f0 user flag 0: the general purpose flag that can be set or cleared by the user. 4 rs1 register bank select bits: 3 rs0 register bank select bits: 2 ov overflow flag: set when a carry was generated from the seventh bit but not from the 8 th bit as a result of the previous operation, or vice-versa. 1 f1 user flag 1: the general purpose flag that can be set or cleared by the user by software. 0 p parity flag: set/cleared by hardware to indicate odd/ even number of 1?s in the accumulator. port 4 bit: 7 6 5 4 3 2 1 0 - - - - p4.3 p4.2 p4.1 p4.0 mnemonic: p4 address: d8h another bit-addressable port p4 is also available and only 4 bits (p4<3:0>) can be used. this port ad- dress is located at 0d8h with the same function as that of port p1, except the p4.3 and p4.2 are alter- native function pins. it can be used as general i/o pins or external interrupt input sources ( int2 , int3 ). accumulator bit: 7 6 5 4 3 2 1 0 acc.7 acc.6 acc.5 acc.4 acc.3 acc.2 acc.1 acc.0 mnemonic: acc address: e0h bit name function 7-0 acc the a or acc register is the standard 8052 accumulator. b register bit: 7 6 5 4 3 2 1 0 b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 mnemonic: b address: f0h bit name function
w78e054d/w78e052d/w78e051d data sheet - 34 - 7-0 b the b register is the standard 8052 r egister that serves as a second accumulator.
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 35 - revision a10 10 instruction the w78e054d/w78e052d/w78e051d series execute all the instructions of the standard 8052 fam- ily. the operations of these instructions, as well as their effects on flag and status bits, are exactly the same. op-code hex code bytes w78e054d/w78e052d/w78e051d series clock cycles nop 00 1 12 add a, r0 28 1 12 add a, r1 29 1 12 add a, r2 2a 1 12 add a, r3 2b 1 12 add a, r4 2c 1 12 add a, r5 2d 1 12 add a, r6 2e 1 12 add a, r7 2f 1 12 add a, @r0 26 1 12 add a, @r1 27 1 12 add a, direct 25 2 12 add a, #data 24 2 12 addc a, r0 38 1 12 addc a, r1 39 1 12 addc a, r2 3a 1 12 addc a, r3 3b 1 12 addc a, r4 3c 1 12 addc a, r5 3d 1 12 addc a, r6 3e 1 12 addc a, r7 3f 1 12 addc a, @r0 36 1 12 addc a, @r1 37 1 12 addc a, direct 35 2 12 addc a, #data 34 2 12 subb a, r0 98 1 12 subb a, r1 99 1 12 subb a, r2 9a 1 12 subb a, r3 9b 1 12
w78e054d/w78e052d/w78e051d data sheet - 36 - op-code hex code bytes w78e054d/w78e052d/w78e051d series clock cycles subb a, r4 9c 1 12 subb a, r5 9d 1 12 subb a, r6 9e 1 12 subb a, r7 9f 1 12 subb a, @r0 96 1 12 subb a, @r1 97 1 12 subb a, direct 95 2 12 subb a, #data 94 2 12 inc a 04 1 12 inc r0 08 1 12 inc r1 09 1 12 inc r2 0a 1 12 inc r3 0b 1 12 inc r4 0c 1 12 inc r5 0d 1 12 inc r6 0e 1 12 inc r7 0f 1 12 inc @r0 06 1 12 inc @r1 07 1 12 inc direct 05 2 12 inc dptr a3 1 24 dec a 14 1 12 dec r0 18 1 12 dec r1 19 1 12 dec r2 1a 1 12 dec r3 1b 1 12 dec r4 1c 1 12 dec r5 1d 1 12 dec r6 1e 1 12 dec r7 1f 1 12 dec @r0 16 1 12 dec @r1 17 1 12 dec direct 15 2 12
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 37 - revision a10 op-code hex code bytes w78e054d/w78e052d/w78e051d series clock cycles mul ab a4 1 48 div ab 84 1 48 da a d4 1 12 anl a, r0 58 1 12 anl a, r1 59 1 12 anl a, r2 5a 1 12 anl a, r3 5b 1 12 anl a, r4 5c 1 12 anl a, r5 5d 1 12 anl a, r6 5e 1 12 anl a, r7 5f 1 12 anl a, @r0 56 1 12 anl a, @r1 57 1 12 anl a, direct 55 2 12 anl a, #data 54 2 12 anl direct, a 52 2 12 anl direct, #data 53 3 24 orl a, r0 48 1 12 orl a, r1 49 1 12 orl a, r2 4a 1 12 orl a, r3 4b 1 12 orl a, r4 4c 1 12 orl a, r5 4d 1 12 orl a, r6 4e 1 12 orl a, r7 4f 1 12 orl a, @r0 46 1 12 orl a, @r1 47 1 12 orl a, direct 45 2 12 orl a, #data 44 2 12 orl direct, a 42 2 12 orl direct, #data 43 3 24 xrl a, r0 68 1 12
w78e054d/w78e052d/w78e051d data sheet - 38 - op-code hex code bytes w78e054d/w78e052d/w78e051d series clock cycles xrl a, r1 69 1 12 xrl a, r2 6a 1 12 xrl a, r3 6b 1 12 xrl a, r4 6c 1 12 xrl a, r5 6d 1 12 xrl a, r6 6e 1 12 xrl a, r7 6f 1 12 xrl a, @r0 66 1 12 xrl a, @r1 67 1 12 xrl a, direct 65 2 12 xrl a, #data 64 2 12 xrl direct, a 62 2 12 xrl direct, #data 63 3 24 clr a e4 1 12 cpl a f4 1 12 rl a 23 1 12 rlc a 33 1 12 rr a 03 1 12 rrc a 13 1 12 swap a c4 1 12 mov a, r0 e8 1 12 mov a, r1 e9 1 12 mov a, r2 ea 1 12 mov a, r3 eb 1 12 mov a, r4 ec 1 12 mov a, r5 ed 1 12 mov a, r6 ee 1 12 mov a, r7 ef 1 12 mov a, @r0 e6 1 12 mov a, @r1 e7 1 12 mov a, direct e5 2 12 mov a, #data 74 2 12 mov r0, a f8 1 12
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 39 - revision a10 op-code hex code bytes w78e054d/w78e052d/w78e051d series clock cycles mov r1, a f9 1 12 mov r2, a fa 1 12 mov r3, a fb 1 12 mov r4, a fc 1 12 mov r5, a fd 1 12 mov r6, a fe 1 12 mov r7, a ff 1 12 mov r0, direct a8 2 24 mov r1, direct a9 2 24 mov r2, direct aa 2 24 mov r3, direct ab 2 24 mov r4, direct ac 2 24 mov r5, direct ad 2 24 mov r6, direct ae 2 24 mov r7, direct af 2 24 mov r0, #data 78 2 12 mov r1, #data 79 2 12 mov r2, #data 7a 2 12 mov r3, #data 7b 2 12 mov r4, #data 7c 2 12 mov r5, #data 7d 2 12 mov r6, #data 7e 2 12 mov r7, #data 7f 2 12 mov @r0, a f6 1 12 mov @r1, a f7 1 12 mov @r0, direct a6 2 24 mov @r1, direct a7 2 24 mov @r0, #data 76 2 12 mov @r1, #data 77 2 12 mov direct, a f5 2 12 mov direct, r0 88 2 24 mov direct, r1 89 2 24
w78e054d/w78e052d/w78e051d data sheet - 40 - op-code hex code bytes w78e054d/w78e052d/w78e051d series clock cycles mov direct, r2 8a 2 24 mov direct, r3 8b 2 24 mov direct, r4 8c 2 24 mov direct, r5 8d 2 24 mov direct, r6 8e 2 24 mov direct, r7 8f 2 24 mov direct, @r0 86 2 24 mov direct, @r1 87 2 24 mov direct, direct 85 3 24 mov direct, #data 75 3 24 mov dptr, #data 16 90 3 24 movc a, @a+dptr 93 1 24 movc a, @a+pc 83 1 24 movx a, @r0 e2 1 24 movx a, @r1 e3 1 24 movx a, @dptr e0 1 24 movx @r0, a f2 1 24 movx @r1, a f3 1 24 movx @dptr, a f0 1 24 push direct c0 2 24 pop direct d0 2 24 xch a, r0 c8 1 12 xch a, r1 c9 1 12 xch a, r2 ca 1 12 xch a, r3 cb 1 12 xch a, r4 cc 1 12 xch a, r5 cd 1 12 xch a, r6 ce 1 12 xch a, r7 cf 1 12 xch a, @r0 c6 1 12 xch a, @r1 c7 1 12 xchd a, @r0 d6 1 12 xchd a, @r1 d7 1 12
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 41 - revision a10 op-code hex code bytes w78e054d/w78e052d/w78e051d series clock cycles xch a, direct c5 2 24 clr c c3 1 12 clr bit c2 2 12 setb c d3 1 12 setb bit d2 2 12 cpl c b3 1 12 cpl bit b2 2 12 anl c, bit 82 2 24 anl c, /bit b0 2 24 orl c, bit 72 2 24 orl c, /bit a0 2 24 mov c, bit a2 2 12 mov bit, c 92 2 24 acall addr11 71, 91, b1, 11, 31, 51, d1, f1 2 24 lcall addr16 12 3 24 ret 22 1 24 reti 32 1 24 ajmp addr11 01, 21, 41, 61, 81, a1, c1, e1 2 24 ljmp addr16 02 3 24 jmp @a+dptr 73 1 24 sjmp rel 80 2 24 jz rel 60 2 24 jnz rel 70 2 24 jc rel 40 2 24 jnc rel 50 2 24 jb bit, rel 20 3 24 jnb bit, rel 30 3 24 jbc bit, rel 10 3 24 cjne a, direct, rel b5 3 24 cjne a, #data, rel b4 3 24
w78e054d/w78e052d/w78e051d data sheet - 42 - op-code hex code bytes w78e054d/w78e052d/w78e051d series clock cycles cjne @r0, #data, rel b6 3 24 cjne @r1, #data, rel b7 3 24 cjne r0, #data, rel b8 3 24 cjne r1, #data, rel b9 3 24 cjne r2, #data, rel ba 3 24 cjne r3, #data, rel bb 3 24 cjne r4, #data, rel bc 3 24 cjne r5, #data, rel bd 3 24 cjne r6, #data, rel be 3 24 cjne r7, #data, rel bf 3 24 djnz r0, rel d8 2 24 djnz r1, rel d9 2 24 djnz r5, rel dd 2 24 djnz r2, rel da 2 24 djnz r3, rel db 2 24 djnz r4, rel dc 2 24 djnz r6, rel de 2 24 djnz r7, rel df 2 24 djnz direct, rel d5 3 24 table 10-1: instruction set for w78e054d/w78e052d/w78e051d
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 43 - revision a10 10.1 instruction timing a machine cycle consists of a sequence of 6 states, numbered s1 through s6. each state time lasts for two oscillator periods. thus a machine cycle take s 12 oscillator periods or 1us if the oscillator fre- quency is 12mhz. each state is divided into a phase 1 half and a phas e 2 half. the fetch/execute sequences in states and phases for various kinds of instructions. normally two program fetches are generated during each machine cycle, even if the instruct ion being executed doesn?t requir e it. if the instruction being exe- cuted doesn?t need more code bytes, the cpu simp ly ignores the extra fetch, and the program counter is not incremented. execution of a one-cycl e instruction begins during state 1 of the machine cycle, when the opcode is latched into the instruction register. a second fetch occurs during s4 of the same machine cycle. execution is complete at the end of state 6 of this machine cycle. the movx instructions take two machine cycles to execute. no program fetch is generated during the second cycle of a movx instruction. this is the only time program fetches are skipped. the fetch/execute sequence for movx instructions. the fetch/execute sequences are the same whether the program memory is internal or external to the chip. execution times do not depend on whether the program memory is internal or external. the signals and timing involved in program fetches when the program memory is external. if program memory is external, then the program memory read strobe psen is normally activated twice per ma- chine cycle. if an access to external data memory occurs, tw o psen pulse are skipped, because the address and data bus are being used for the data memory access. note that a data memory bus cy- cle takes twice as much time as a program memory bus cycle.
w78e054d/w78e052d/w78e051d data sheet - 44 - 11 power management the w78e054d/w78e052d/w78e051d has several featur es that help the user to control the power consumption of the device. the power saved f eatures have basically the power down mode and the idle mode of operation. 11.1 idle mode the user can put the device into idle mode by writing 1 to the bit pcon.0. the instruction that sets the idle bit is the last instruction t hat will be executed before the device goes into idle mode. in the idle mode, the clock to the cpu is halt ed, but not to the interrupt, timer, watchdog timer and serial port blocks. this forces the cpu state to be frozen; the program counter, the stack pointer, the program status word, the accumulator and the other register s hold their contents. the port pins hold the logi- cal states they had at the time idle was activated. the idle mode can be terminated in two ways. since the interrupt controller is still acti ve, the activation of any enabled inte rrupt can wake up the processor. this will automatically clear the idle bit, terminate the idle mode, and the interrupt service routine (isr) will be executed. after the isr, execution of the program will continue from the instruction which put the device into idle mode. the idle mode can also be exited by activating the reset. the device can put into reset either by apply- ing a high on the external rst pin, a power on reset condition or a watchdog timer reset. the exter- nal reset pin has to be held high for at least two machine cycles i.e. 24 clock periods to be recognized as a valid reset. in the reset condition the progra m counter is reset to 0000h and all the sfrs are set to the reset condition. since the clock is already ru nning there is no delay and execution starts imme- diately. 11.2 power down mode the device can be put into power down mode by writ ing 1 to bit pcon.1. the instruction that does this will be the last instruction to be executed before the device goes into power down mode. in the power down mode, all the clocks are stopped and the device comes to a halt. all activity is completely stopped and the power consumption is reduced to the lowest possible value. the port pins output the values held by their respective sfrs. the w78e054d/w78e052d/w78e051d will exit the powe r down mode with a reset or by an external interrupt pin enabled as level detects. an external re set can be used to exit the power down state. the high on rst pin terminates the power down mode, and restarts the clock. the program execution will restart from 0000h. in the power down mode, the clock is stopped, so the watchdog timer cannot be used to provide the reset to exit power down mode. the w78e054d/w78e052d/w78e051d can be woken fr om the power down mode by forcing an ex- ternal interrupt pin activated, provided the corr esponding interrupt is enabled, while the global en- able(ea) bit is set and the external input has been set to a level detect mode. if these conditions are met, then the high level on the external pin re-starts the oscillator. then device executes the interrupt service routine for the corresponding external interrupt. after the interrupt servic e routine is completed, the program execution returns to the instruction a fter one which put the device into power down mode and continues from there.
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 45 - revision a10 12 reset conditions the user has several hardware related options for placing the w78e054d/w78e052d/w78e051d into reset condition. in general, most register bits go to their reset value irrespective of the reset condition, but there are a few flags whose state depends on the so urce of reset. the user can use these flags to determine the cause of reset using software. 12.1 sources of reset 12.1.1 external reset the device continuously samples t he rst pin at state s5p2 of every machine cycle. therefore the rst pin must be held for at least 2 machine cycles (24 clock cycles) to ensure detection of a valid rst high. the reset circuitry then synchronously applies the internal reset signal. thus the reset is a synchronous operation and requires the clock to be running to cause an external reset. for more tim- ing information, please referenc e the character 21.4.5 (page 77). once the device is in reset condition, it will remain so as long as rst is 1. even after rst is deacti- vated, the device will continue to be in reset state for up to two machine cycles, and then begin pro- gram execution from 0000h. there is no flag as sociated with the external reset condition. 12.1.2 software reset the w78e054d/w78e052d/w78e051d offers a software reset to switch back to the aprom. setting chpcon bits 0, 1 and 7 to logic-1 creates softwar e reset to reset the cpu to start aprom code. note: software reset only ldrom jump to apr om, aprom can?t software reset to ldrom. 12.1.3 watchdog timer reset the watchdog timer is a free running timer with prog rammable time-out intervals. the user can clear the watchdog timer at any time, causing it to rest art the count. when the time-out interval is reached an interrupt flag is set. if the watc hdog reset is enabled and the watchdog timer is not cleared, the watchdog timer will generate a reset. this places the device into the reset condition. the reset condi- tion is maintained by hardware for two machine cycl es. once the reset is removed the device will be- gin execution from 0000h. 12.2 reset state most of the sfrs and registers on t he device will go to the same condition in the reset state. the pro- gram counter is forced to 0000h and is held there as long as the reset condition is applied. however, the reset state does not affect the on-chip ram. the data in the ra m will be preserved during the re- set. however, the stack pointer is reset to 07h, and therefore the stack contents will be lost. the ram contents will be lost if the vdd falls below approxima tely 2v, as this is the minimum voltage level re- quired for the ram to operate normally. therefore afte r a first time power on reset the ram contents will be indeterminate. during a power fail condition, if the power falls below 2v, the ram contents are lost. after a reset most sfrs are cleared. interrupts and timers are disabled. the watchdog timer is dis- abled if the reset source was a por. the port sfrs has 0ffh written into them which puts the port pins in a high state.
w78e054d/w78e052d/w78e051d data sheet - 46 - 13 interrupts the w78e054d/w78e052d/w78e051d has a 4 priority level interrupt structure with 8 interrupt sources. each of the interrupt sources has an indi vidual priority bit, flag, interrupt vector and enable bit. in addition, the interrupts can be globally enabled or disabled. 13.1 interrupt sources the external interrupts int0 and int1 can be either edge triggered or level triggered, depending on bits it0 and it1. the bits ie0 and ie1 in the tcon register are the flags which are checked to gener- ate the interrupt. in the edge triggered mode, the in tx inputs are sampled in every machine cycle. if the sample is high in one cycle and low in the nex t, then a high to low transition is detected and the interrupts request flag iex in tcon o is set. the flag bit requests the interrupt. since the external in- terrupts are sampled every machine cycle, they hav e to be held high or low for at least one complete machine cycle. the iex flag is automatically cleared when the service routine is called. if the level trig- gered mode is selected, then the reque sting source has to hold the pin lo w till the interrupt is serviced. the iex flag will not be cleared by the hardware on entering the service r outine. if the interrupt contin- ues to be held low even after the service routine is completed, then the processor may acknowledge another interrupt request from the same s ource. note that the external interrupts int2 and int3 . by default, the individual interrupt flag corresponding to external interrupt 2 to 3 must be cleared manually by software. the timer 0 and 1 interrupts are generated by the tf0 and tf1 flags. these flags are set by the over- flow in the timer 0 and timer 1. the tf0 and tf1 flags are automatically cleared by the hardware when the timer interrupt is serviced. the timer 2 interrupt is generated by a logical or of the tf2 and the exf2 flags. these flags are set by overflow or capture/reload events in the timer 2 operation. the hardware does not clear these flags when a timer 2 in terrupt is executed. software has to resolve the cause of the interrupt between tf2 a nd exf2 and clear the appropriate flag. the serial block can generate interrupts on receptio n or transmission. there are two interrupt sources from the serial block, which are obtained by the ri and ti bits in the scon sfr, these bits are not automatically cleared by the hardw are, and the user will have to cl ear these bits using software. all the bits that generate interrupts can be set or re set by hardware, and thereby software initiated in- terrupts can be generated. each of the individual in terrupts can be enabled or disabled by setting or clearing a bit in the ie sfr. ie also has a global enable/disable bit ea, which can be cleared to dis- able all the interrupts, at once. source vector address source vector address external interrupt 0 0003h timer 0 overflow 000bh external interrupt 1 0013h timer 1 overflow 001bh serial port 0023h timer 2 overflow 002bh external interrupt 2 0033h external interrupt 3 003bh table 13?1 w78e054d/w78e052d/w78e051d interrupt vector table 13.2 priority level structure there are 4 priority levels for the interrupts high, low. naturally, a hi gher priority interrupt cannot be interrupted by a lower priority interrupt. however th ere exists a pre-defined hierarchy amongst the in- terrupts themselves. this hierarchy comes into play when the interrupt controller has to resolve simul- taneous requests having the same priority level. this hierarchy is defined as shown on table.
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 47 - revision a10 priority bits iph ip/ xicon.7/ xicon.3 interrupt priority level 0 0 level 0 (lowest priority) 0 1 level 1 1 0 level 2 1 1 level 3 (highest priority) the interrupt flags are sampled every machine cycle. in the same machine cycle, the sampled inter- rupts are polled and their priority is resolved. if certain conditions are met then the hardware will exe- cute an internally generated lcall instruction which will vector the process to the appropriate inter- rupt vector address. the conditi ons for generating the lcall are; 1. an interrupt of equal or higher prio rity is not current ly being serviced. 2. the current polling cycle is the last machine cycle of the instruction currently being executed. 3. the current instruction does not involve a write to ie, ip, iph, xicon registers and is not a reti. if any of these conditions are not met, then the lc all will not be generated. the polling cycle is re- peated every machine cycle, with the interrupts sampled in the same machine cycle. if an interrupt flag is active in one cycle but not responded to, and is not active when the above conditions are met, the denied interrupt will not be serviced. this means that active interrupts are not remembered; every poll- ing cycle is new. the processor responds to a valid interrupt by ex ecuting an lcall instruction to the appropriate ser- vice routine. this may or may not clear the flag which caused the interrupt. in case of timer interrupts, the tf0 or tf1 flags are cleared by hardware whene ver the processor vectors to the appropriate timer service routine. in case of external interrupt, /in t0 and /int1, the flags are cleared only if they are edge triggered. in case of serial interrupts, the flags are not cleared by hardwar e. in the case of timer 2 interrupt, the flags are not cleared by hardware. the hardware lcall behaves exactly like the soft- ware lcall instruction. this instruction saves t he program counter contents onto the stack, but does not save the program status word psw. the pc is reloaded with the vector address of that interrupt which caused the lcall. these address of vector for the different sources are as shown on the below table. the vector table is not evenly spaced; this is to accommodate future expansions to the device family. execution continues from the vect ored address till an reti instructi on is executed. on execution of the reti instruction the pr ocessor pops the stack and loads the pc with the contents at the top of the stack. the user must take care t hat the status of the st ack is restored to what is after the hardware lcall, if the execution is to return to the inte rrupted program. the processor does not notice anything if the stack contents are modified and will proceed with ex ecution from the address put back into pc. note that a ret instruction would perform exactly the same process as a re ti instruction, but it would not inform the interrupt controller that the interrupt service routine is completed, and would leave the controller still thinking that the service rout ine is underway. each interrupt source can be individually enabled or di sabled by setting or clearing a bit in registers ie. the ie register also contains a global disable bit, ea, which disables all interrupts at once.
w78e054d/w78e052d/w78e051d data sheet - 48 - each interrupt source can be individually programmed to one of 2 priority levels by setting or clearing bits in the ip registers. an inte rrupt service routine in progress ca n be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. the highest priority interrupt service cannot be interrupted by any other interrupt source. so , if two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if requests of the same priority level are receiv ed simultaneously, an internal polling sequence deter- mines which request is serviced. this is called the ar bitration ranking. note that the arbitration ranking is only used to resolve simultaneous req uests of the same priority level. table below summarizes the interrupt sources, flag bi ts, vector addresses, enable bits, priority bits, arbitration ranking, and external interrupt may wake up the cpu from power down mode. source flag vector address enable bit interrupt priority flag cleared by arbitration ranking power- down wakeup external interrupt 0 ie0 0003h ex0 (ie.0) iph.0, ip.0 hardware, software 1(highest) yes timer 0 overflow tf0 000bh et0 (ie.1) iph.1, ip.1 hardware, software 2 no external interrupt 1 ie1 0013h ex1 (ie.2) iph.2, ip.2 hardware, software 3 yes timer 1 overflow tf1 001bh et1 (ie.3) iph.3, ip.3 hardware, software 4 no serial port ri + ti 0023h es (ie.4) iph.4, ip.4 software 5 no timer 2 over- flow/match tf2 002bh et2 (ie.5) iph.5, ip.5 software 6 no external interrupt 2 ie2 0033h ex2 (xicon.2) iph.6, px2 hardware, software 7 yes external interrupt 3 ie3 003bh ex3 (xicon.6) iph.7, px3 hardware, software 8(lowest) yes table 13?2 summary of interrupt sources 13.3 interrupt response time the response time for each interrupt source depends on several factors, such as the nature of the in- terrupt and the instruction underway. in the case of external interrupts int0 and int1 , they are sam- pled at s5p2 of every machine cycle and then their corresponding interrupt flags iex will be set or re- set. the timer 0 and 1 overflow flags are set at c3 of the machine cycle in which overflow has oc- curred. these flag values are polled only in the next machine cycle. if a request is active and all three conditions are met, then the hardware generated lcall is executed. this lcall itself takes four ma- chine cycles to be completed. thus there is a minimum time of five machine cycles between the inter- rupt flag being set and the interrupt service routine being executed. a longer response time should be anticipated if any of the three conditions are not met. if a higher or equal priority is being serviced, then the interrupt latency time obviously depends on the nature of the
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 49 - revision a10 service routine currently being executed. if the polling cycle is not the last mach ine cycle of the instruc- tion being executed, then an additional delay is intr oduced. the maximum response time (if no other interrupt is in service) occurs if the device is performing a write to ie, ip, iph and then executes a mul or div instruction. 13.4 interrupt inputs since the external interrupt pins are sampled once each machine cycle, an input high or low should hold for at least one machine cycle to ensure proper sampling. if the external interrupt is high for at least one machine cycle, and then hold it low for at least one machine cycle. this is to ensure that the transition is seen and that interrupt request flag ie n is set. ien is automatically cleared by the cpu when the service routine is called. if the external interrupt is level-activated, the ex ternal source must hold the request active until the requested interrupt is actually generated. if the exte rnal interrupt is still asserted when the interrupt service routine is completed another interrupt will be generated. it is not necessary to clear the inter- rupt flag ien when the interrupt is level sens itive, it simply tracks the input pin level. if an external interrupt is enabled when the w7 8e054d/w78e052d/w78e051d is put into power down or idle mode, the interrupt will cause the pr ocessor to wake up and resume operation. refer to the section on power reduction modes for details.
w78e054d/w78e052d/w78e051d data sheet - 50 - 14 programmable timers/counters the w78e054d/w78e052d/w78e051d series have three 16-bit programmable timer/counters. a machine cycle equals 12 or 6 oscillator periods, and it depends on 12t mode or 6t mode that the user configured this device. 14.1 timer/counters 0 & 1 w78e054d/w78e052d/w78e051d has two 16-bit ti mer/counters. each of these timer/counters has two 8 bit registers which form the 16 bit counti ng register. for timer/count er 0 they are th0, the upper 8 bits register, and tl0, the lower 8 bit regist er. similarly timer/counter 1 has two 8 bit regis- ters, th1 and tl1. the two can be configured to opera te either as timers, counting machine cycles or as counters counting external inputs. when configured as a "timer", the timer counts clock cycles. the timer clock can be programmed to be thought of as 1/12 of the system clock. in t he "counter" mode, the register is incremented on the falling edge of the external input pin, t0 in case of timer 0, and t1 for timer 1. the t0 and t1 inputs are sampled in every machine cycle at c4. if the sampled value is high in one machine cycle and low in the next, then a valid high to low transition on the pin is recognized and the count register is incre- mented. since it takes two machine cycles to rec ognize a negative transition on the pin, the maximum rate at which counting will take place is 1/24 of the master clock frequency. in either the "timer" or "counter" mode, the count register will be updated at c3. therefore, in the "timer" mode, the recog- nized negative transition on pin t0 and t1 can caus e the count register value to be updated only in the machine cycle following the one in which the negative edge was detected. the "timer" or "counter" function is selected by the " tc/ " bit in the tmod special function register. each timer/counter has one selection bit for its ow n; bit 2 of tmod selects the function for tim- er/counter 0 and bit 6 of tmod selects the function for timer/counter 1. in addition each tim- er/counter can be set to operate in any one of fo ur possible modes. the mode selection is done by bits m0 and m1 in the tmod sfr. 14.2 time-base selection w78e054d/w78e052d/w78e051d provides users with two modes of operation for the timer. the timers can be programmed to operat e like the standard 8051 family, counti ng at the rate of 1/12 of the clock speed. this will ensure that timing loops on w78e054d/w 78e052d/w78e051d and the stan- dard 8051 can be matched. this is the default mode of operation of the w78e054d/w78e052d/w78e051d timers. 14.2.1 mode 0 in mode 0, the timer/counter is a 13-bit counter. the 13-bit counter consists of thx (8 msb) and the five lower bits of tlx (5 lsb). the upper three bits of tlx are ignored. the timer/counter is enabled when trx is set and either gate is 0 or intx is 1. when tc / is 0, the timer/counter counts clock cycles; when tc / is 1, it counts falling edges on t0 (timer 0) or t1 (timer 1). for clock cycles, the time base be 1/12 speed, and the falling edge of the clock increments the counter. when the 13-bit value moves from 1fffh to 0000h, the timer overflow flag tfx is set, and an interrupt occurs if en- abled. 14.2.2 mode 1 mode 1 is similar to mode 0 except that the counting register forms a 16-bit counter, rather than a 13- bit counter. this means that all the bits of thx and tlx are used. roll-over occurs when the timer moves from a count of 0ffffh to 0000h. the timer over flow flag tfx of the relevant timer is set and if
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 51 - revision a10 enabled an interrupt will occur. the selection of the ti me-base in the timer mode is similar to that in mode 0. the gate function operates similarly to that in mode 0. 1/12 fosc t0=p3.4 (t1=p3.5) 0 1 tr0=tcon.4 (tr1=tcon.6) gate=tmod.3 (gate=tmod.7) int0 =p3.2 (int1 =p3.3) c/t =tmod.2 (c/t =tmod.6) 07 07 tfx interrupt tl0 (tl1) th0 (th1) tf0 (tf1) 4 m1, m0=tmod.1, tmod.0 (m1, m0=tmod.5, tmod.4) 00 01 figure 14?1 timer/counters 0 & 1 in mode 0, 1 14.2.3 mode 2 in mode 2, the timer/counter is in the auto reload mode. in this mode, tlx acts as an 8-bit count reg- ister, while thx holds the reload value. when the tlx register overflows from ffh to 00h, the tfx bit in tcon is set and tlx is reloaded with the conten ts of thx, and the counti ng process continues from here. the reload operation leaves t he contents of the thx register unchanged. counting is enabled by the trx bit and proper setting of gate and intx pins. as in the other two modes 0 and 1 mode 2 allows counting of clock/12 or pulses on pin tn. 1/12 fosc t0=p3.4 (t1=p3.5) 0 1 tr0=tcon.4 (tr1=tcon.6) gate=tmod.3 (gate=tmod.7) int0 =p3.2 (int1 =p3.3) c/t =tmod.2 (c/t =tmod.6) 07 07 tfx interrupt tl0 (tl1) th0 (th1) tf0 (tf1) figure 14?2 timer/counter 0 & 1 in mode 2 14.2.4 mode 3 mode 3 has different operating methods for the two timer/counters. for timer/counter 1, mode 3 simply freezes the counter. timer/counter 0, however, conf igures tl0 and th0 as two separate 8 bit count registers in this mode. the logic for this mode is shown in the figure. tl0 uses the timer/counter 0
w78e054d/w78e052d/w78e051d data sheet - 52 - control bits tc/ , gate, tr0, int0 and tf0. the tl0 can be used to count clock cycles (clock/12) or 1-to-0 transitions on pin t0 as determined by c/t (tmod.2). th0 is forced as a clock cycle counter (clock/12) and takes over the use of tr1 and tf1 from timer/counter 1. mode 3 is used in cases where an extra 8 bit timer is needed. with timer 0 in mode 3, timer 1 can still be used in modes 0, 1 and 2, but its flexibility is somewhat limited. while it s basic functionality is maintained, it no longer has control over its overflow flag tf1 and the enable bit tr1. timer 1 can still be used as a timer/counter and retains the use of gate and int1 pin. in this condition it can be turned on and off by switching it out of and into its own mode 3. it can also be used as a baud rate generator for the serial port. figure 14?3 timer/counter mode 3 14.3 timer/counter 2 timer/counter 2 is a 16 bit up/down counter which is configured by the t2mod(bit 0) register and controlled by the t2con register. timer/counter 2 is equipped with a capture/reload capability. as with the timer 0 and timer 1 counters, there exists considerable flexibility in selecting and controlling the clock, and in defining the operating mode. the clock source for timer/counter 2 may be selected for either the external t2 pin (c/t2 = 1) or the cr ystal oscillator, which is divided by 12 (c/t2 = 0). the clock is then enabled when tr2 is a 1, and disabled when tr2 is a 0. 14.3.1 capture mode the capture mode is enabled by setting the cp rl /2 bit in the t2con register to a 1. in the capture mode, timer/counter 2 serves as a 16 bit up counte r. when the counter rolls over from 0ffffh to 0000h, the tf2 bit is set, which will generate an inte rrupt request. if the exen2 bit is set, then a nega- tive transition of t2ex pin will cause the value in the tl2 and th2 register to be captured by the rcap2l and rcap2h register s. this action also causes the exf2 bit in t2con to be set, which will also generate an interrupt. (rclk,tclk, rl2cp / )= (0,0,1)
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 53 - revision a10 figure 14?4 16-bit capture mode 14.3.2 auto-reload mode, counting up the auto-reload mode as an up counter is enabled by clearing the cp rl /2 bit in the t2con register and clearing the dcen bit in t2mod(bit0) register. in this mode, timer/counter 2 is a 16 bit up coun- ter. when the counter rolls over from 0ffffh, a rel oad is generated that causes the contents of the rcap2l and rcap2h registers to be reloaded into t he tl2 and th2 registers. the reload action also sets the tf2 bit. if the exen2 bit is set, then a negative transition of t2ex pin will also cause a reload. this action also sets the exf2 bit in t2con. (rclk,tclk, rl2cp / )= (0,0,0) & dcen= 0 t2=p1.0 0 1 c/t2 =t2con.1 timer2 interrupt t2con.6 tr2=t2con.2 t2con.7 figure 14?5 16-bit auto-reload mode, counting up 14.3.3 auto-reload mode, counting up/down timer/counter 2 will be in auto-reload mode as an up/down counter if cp rl /2 bit in t2con is cleared and the dcen bit in t2mod is set. in th is mode, timer/counter 2 is an up/down counter whose direction is controlled by the t2ex pin. a 1 on this pin cause the counter to count up. an over- flow while counting up will cause the counter to be re loaded with the contents of the capture registers. the next down count following the case where the contents of timer/counter equal the capture regis- ters will load a 0ffffh into timer/counter 2. in either event a reload will set the tf2 bit. a reload will also toggle the exf2 bit. however, the exf2 bit c annot generate an interrupt while in this mode.
w78e054d/w78e052d/w78e051d data sheet - 54 - (rclk,tclk, rl2cp / )= (0,0,0) & dcen= 1 t2=p1.0 0 1 t2ex=p1.1 c/t2 =t2con.1 timer2 interrupt t2con.6 tr2=t2con.2 t2con.7 down counting reload value up counting reload value figure 14?6 16-bit auto-reload mode, counting up 14.3.4 baud rate generator mode the baud rate generator mode is enabled by setting ei ther the rclk or tclk bits in t2con register. while in the baud rate generator mode, timer/counter 2 is a 16 bit counter with auto reload when the count rolls over from 0ffffh. however, rolling over does not set the tf2 bit. if exen2 bit is set, then a negative transition of the t2ex pin will set exf2 bit in the t2con register and cause an interrupt request. rclk+tclk=1, rl2cp / =0 figure 14?7 baud rate generator mode
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 55 - revision a10 15 watchdog timer the watchdog timer is a free-running timer which ca n be programmed by the user to serve as a sys- tem monitor, a time-base generator or an event timer. it is basically a set of dividers that divide the system clock. the divider output is selectable and determines the time-out interval. when the time-out occurs a system reset can also be caused if it is enabled. the main use of the watchdog timer is as a system monitor. this is important in real-time control applications. in case of power glitches or electro- magnetic interference, the processor may begin to execute errant code. if th is is left unchecked the entire system may crash. the watchd og time-out selection will result in different time-out values de- pending on the clock speed. the watchdog timer will de disabled on reset. in general, software should restart the watchdog timer to put it into a known st ate. the control bits that support the watchdog tim- er are discussed below. enw : enable watchdog if set. clrw : clear watchdog timer an d pre-scalar if set. this fl ag will be cleared automatically widl : if this bit is set, watch-dog is enabled under idle mode. if cleared, watchdog is disabled un- der idle mode. default is cleared. ps2, ps1, ps0: watchdog pre-sc alar timer select. pre-scalar is selected when set ps2 ? 0 as follows: ps2 ps1 ps0 pre-scalar select 0 0 0 2 0 0 1 8 0 1 0 4 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256 the time-out period is obtained using the following equation for 12t per machine cycle: ms scalare osc 121000 pr2 1 14 ? before watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to wdtc.6 (clrw). after 1 is written to this bit, the 14-bit timer, pre-scalar and this bit will be reset on the next instruction cycle. the watchdog timer is cleared on reset.
w78e054d/w78e052d/w78e051d data sheet - 56 - figure 15?1 watchdog timer block diagram typical watch-dog time-out period when osc = 20 mhz ps2 ps1 ps0 watchdog time-out period (for 12t per machine cycle) 0 0 0 19.66 ms 0 1 0 78.64 ms 0 0 1 39.32 ms 0 1 1 157.28 ms 1 0 0 314.57 ms 1 0 1 629.14 ms 1 1 0 1.25 s 1 1 1 2.50 s table 15?2 watch-dog time-out period for 12t per machine cycle, 20mhz ps2 ps1 ps0 watchdog time-out period (for 6t per machine cycle) 0 0 0 9.83 ms 0 1 0 39.32 ms 0 0 1 19.66 ms 0 1 1 78.64 ms 1 0 0 157.28 ms 1 0 1 314.57ms 1 1 0 629.14 ms 1 1 1 1.250 s table 15?3 watch-dog time-out period for 6t per machine cycle, 20mhz
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 57 - revision a10 16 serial port serial port in this device is a full duplex port. the serial port is capable of synchronous as well as asynchronous communication. in synchronous mode the device generates the clock and operates in a half-duplex mode. in the asynchronous mode, full duplex operation is available. this means that it can simultaneously transmit and receive data. the tr ansmit register and the receive buffer are both ad- dressed as sbuf special function register. however any write to sbuf will be to the transmit regis- ter, while a read from sbuf will be from the receiver buffer register. the serial port can operate in four different modes as described below. 16.1 mode 0 this mode provides synchronous communication with external devices. in this mode serial data is transmitted and received on the rxd line. txd is used to transmit the shift clock. the txd clock is provided by the device whether it is transmitting or receiving. this mode is therefore a half-duplex mode of serial communication. in this mode, 8 bits are transmitted or received per frame. the lsb is transmitted/received first. the baud rate is fixed at 1/ 12 of the oscillator frequency. this baud rate is determined by the sm2 bit (scon.5). when this bit is set to 0, then the serial port runs at 1/12 of the clock. this additional facility of programmable baud rate in mode 0 is the only difference between the standard 8051 and w78e054d/w78e052d/w78e051d. the functional block diagram is shown below. data enters and leaves the serial port on the rxd line. the txd line is used to output the shift clock. the shift clock is used to shift data into and out of this device and the device at the other end of the line. any instruction that causes a write to sbuf will start the transmission. the shift clock w ill be activated and data will be shi fted out on the rxd pin till all 8 bits are transmitted. if sm2 = 1, then the data on rxd will appear 1 clock period before the falling edge of shift clock on txd. the clock on txd then re mains low for 2 clock periods, and then goes high again. if sm2 = 0, the data on rxd will appear 3 cloc k periods before the falling edge of shift clock on txd. the clock on txd then remains low for 6 cloc k periods, and then goes high again. this ensures that at the receiving end the data on rxd line can ei ther be clocked on the rising edge of the shift clock on txd or latched when the txd clock is low.
w78e054d/w78e052d/w78e051d data sheet - 58 - figure 16?1 serial port mode 0 the ti flag is set high in s6p2 following the end of tr ansmission of the last bit. the serial port will re- ceive data when ren is 1 and ri is zero. the shift clock (txd) will be activated and the serial port will latch data on the rising edge of shift clock. the external device should therefore present data on the falling edge on the shift clock. this process continues till all the 8 bi ts have been rece ived. the ri flag is set in s6p2 following the last rising edge of the sh ift clock on txd. this will stop reception, till the ri is cleared by software. 16.2 mode 1 in mode 1, the full duplex asynchronous mode is used. serial communication frames are made up of 10 bits transmitted on txd and received on rxd. the 10 bi ts consist of a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into rb8 in the sfr scon. the baud rate in this mode is variable. the serial baud can be programmed to be 1/16 or 1/32 of the timer 1 overflow. since the timer 1 can be set to different reload values, a wide variation in baud rates is possible. transmission begins with a write to sbuf. the serial data is brought out on to txd pin at s6p2 follow- ing the first roll-over of divide by 16 counter. the ne xt bit is placed on txd pin at s6p2 following the next rollover of the divide by 16 counter. thus the transmission is synchronized to the divide by 16 counter and not directly to the write to sbuf signal. after all 8 bits of data ar e transmitted, the stop bit is transmitted. the ti flag is set in the s6p2 st ate after the stop bit has been put out on txd pin. this will be at the 10th rollover of the divide by 16 counters after a write to sbuf. reception is enabled only if ren is high. the serial por t actually starts the re ceiving of serial data, with the detection of a falling edge on the rxd pin. t he 1-to-0 detector continuously monitors the rxd line, sampling it at the rate of 16 times the se lected baud rate. when a falling edge is detected, the divide by 16 counters is immediately reset. this help s to align the bit boundaries with the rollovers of the divide by 16 counters.
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 59 - revision a10 the 16 states of the counter effect ively divide the bit time into 16 slices. the bit detection is done on a best of three basis. the bit detector samples the rxd pin, at the 8th, 9th and 10th counter states. by using a majority 2 of 3 voting system, the bit value is selected. this is done to improve the noise rejec- tion feature of the serial port. if the first bit detect ed after the falling edge of rxd pin is not 0, then this indicates an invalid start bit, and the reception is immediately aborted. the serial port again looks for a falling edge in the rxd line. if a valid start bit is detected, then the rest of t he bits are also detected and shifted into the sbuf. after shifting in 8 data bits, there is one more shift to do, after which the sbuf and rb8 are loaded and ri is set. however certain conditions must be met before the loading and setting of ri can be done. 1. ri must be 0 and 2. either sm2 = 0, or the received stop bit = 1. if these conditions are met, then the stop bit goes to rb8, the 8 data bits go into sbuf and ri is set. otherwise the received frame may be lost. after the mi ddle of the stop bit, the receiver goes back to looking for a 1-to-0 transition on the rxd pin. 1/2 1/16 tx clock rx clock ti ri tx shift tx start rx shift load sbuf smod clock sin d8 sbuf read sbuf internal data bus serial controllor clock load parin tx start internal data bus write to sbuf sout transmit shift register serial interrupt txd rxd parout rb8 start stop 0 1 bit detector 1-to-0 detector sample 1/16 0 timer 1 overflow 1 receive shift register 01 01 tclk rclk timer 2 overflow figure 16?2 serial port mode 1 16.3 mode 2 this mode uses a total of 11 bits in asynchrono us full-duplex communication. the functional descrip- tion is shown in the figure below. the frame consists of one start bit (0), 8 data bits (lsb first), a pro- grammable 9th bit (tb8) and a stop bit (1). the 9th bit received is put into rb8. the baud rate is pro-
w78e054d/w78e052d/w78e051d data sheet - 60 - grammable to 1/32 or 1/64 of the oscillator frequen cy, which is determined by the smod bit in pcon sfr. transmission begins with a write to sbuf. the serial data is brought out on to txd pin at s6p2 following the first roll-over of the divide by 16 count er. the next bit is placed on txd pin at s6p2 fol- lowing the next rollover of the divide by 16 counter. thus the transmission is synchronized to the di- vide by 16 counters, and not directly to the write to sbuf signal. after all 9 bits of data are transmitted, the stop bit is transmitted. the ti flag is set in the s6p2 state after the stop bit has been put out on txd pin. this will be at the 11th rollover of the di vide by 16 counters after a write to sbuf. reception is enabled only if ren is high. the serial port actual ly starts the receiving of serial data, with the de- tection of a falling edge on the rxd pin. the 1-to-0 de tector continuously monitors the rxd line, sam- pling it at the rate of 16 times the selected baud rate. when a falling edge is detected, the divide by 16 counters is immediately reset. this helps to align the bit boundaries with the rollovers of the divide by 16 counters. the 16 states of the co unter effectively divide the bit time into 16 slices. the bit detection is done on a best of three basis. the bit detector samples the rxd pin, at the 8th, 9th and 10th coun- ter states. by using a majority 2 of 3 voting system, the bit value is selected. this is done to improve the noise rejection feature of the serial port. 1/2 1/16 tx clock rx clock ti ri tx shift tx start rx shift load sbuf smod clock sin d8 sbuf read sbuf internal data bus serial controllor clock load parin tx start internal data bus write to sbuf sout transmit shift register serial interrupt txd rxd parout rb8 start stop 0 1 bit detector 1-to-0 detector sample 1/16 0 fosc/2 1 d8 tb8 receive shift register figure 16?3 serial port mode 2 if the first bit detected after the falling edge of rxd pin, is not 0, then this indicates an invalid start bit, and the reception is immediately aborted. the serial port again looks for a falling edge in the rxd line. if a valid start bit is detected, then the rest of the bits are also detected and shifted into the sbuf. af- ter shifting in 9 data bits, there is one more shift to do, after which the sbuf and rb8 are loaded and ri is set. however certain conditions must be met before the loading and setting of ri can be done. 1. ri must be 0 and 2. either sm2 = 0, or the received stop bit = 1.
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 61 - revision a10 if these conditions are met, then the stop bit goes to rb8, the 8 data bits go into sbuf and ri is set. otherwise the received frame may be lost. after the mi ddle of the stop bit, the receiver goes back to looking for a 1-to-0 transition on the rxd pin. mode 3 this mode is similar to mode 2 in all respects, ex cept that the baud rate is programmable. the user must first initialize the serial related sfr scon before any communication can take place. this in- volves selection of the mode and baud rate. the ti mer 1 should also be initialized if modes 1 and 3 are used. in all four modes, transmission is starte d by any instruction that uses sbuf as a destination register. reception is initiated in mode 0 by t he condition ri = 0 and ren = 1. this will generate a clock on the txd pin and shift in 8 bits on the rxd pi n. reception is initiated in the other modes by the incoming start bit if ren = 1. the external device will start the comm unication by transmitting the start bit. figure 16?4 serial port mode 3 sm0 sm1 mode type baud clock frame size start bit stop bit 9th bit function 0 0 0 synch. 4 or 12 tclks 8 bits no no none 0 1 1 asynch. timer 1 or 2 10 bits 1 1 none 1 0 2 asynch. 32 or 64 tclks 11 bits 1 1 0, 1 1 1 3 asynch. timer 1 or 2 11 bits 1 1 0, 1 table 16?5 serial ports modes
w78e054d/w78e052d/w78e051d data sheet - 62 - 17 flash rom code boot mod e slection the w78e054d/w78e052d/w78e051d boots from aprom program (16k/8k/4k bytes) or ldrom program (2k bytes) at power on reset or external reset. boot mode select by config bits cbs (config.2) config boot select at power-on reset and external reset. 1: boot from aprom (0x0000). 0: boot from ldrom (0x3800).
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 63 - revision a10 18 isp (in-system programming) isp is the ability of program mcu to be programm ed while f/w code in ap-r om or ld-rom. (note: timer 0 for program, erase, read on isp mode. isp operation voltage 3.3- 5.5v) start setting control registers mov sfrcn,#3fh mov sfrfd,#abh mov sfral,#ffh mov sfrah,#ffh mov chpcon,#03h setting timer (about 450 us) and enable timer interrupt start timer and enter idle mode. (cpu will be wakened from idle mode by timer interrupt, then enter in-system programming mode) part 1:2kb aprom procedure of entering in-system programming mode execute the normal application program enter in-system programming mode ? (conditions depend on user's application) end yes go no
w78e054d/w78e052d/w78e051d data sheet - 64 - go timer interrupt service routine: stop timer & disable interrupt end of programming end of erase operation. cpu will be wakened by timer interrupt. setting timer and enable timer interrupt for wake-up . (15 ms for erasing operation) start timer and enter idle mode. (erasing...) part 2: procedure of updating the 2kb aprom is f02k boot mode? setting erase operation mode: mov erpage,#02h mov sfrcn,#22h (erase 2kb aprom isp ) pgm no yes
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 65 - revision a10 pgm read_device_id mov sfrcn,#0ch mov chpcon,#03h setting timer and enable timer interrupt for wake-up . (50us for program operation) read_vt mov sfrcn,#0dh mov sfral,#01h mov sfrah,#00h mov chpcon,#03h . part 2: procedure of updating the 2kb aprom end of programming ? get the parameters of new code (address and data bytes) through i/o ports, uart or other interfaces . setting control registers for programming: mov sfrah,#address_h mov sfral,#address_l mov sfrfd,#data mov sfrcn,#21h no yes read_compay_id ov sfrcn,#0bh mov chpcon,#03h read_dist mov sfrcn,#0eh mov sfral,#02h mov sfrah,#00h mov chpcon,#03h . is currently in the f02k boot mode ? ease 14k ap programming: mov erpage,#01 mov sfrcn,#22h
w78e054d/w78e052d/w78e051d data sheet - 66 - pgm software reset cpu and re-boot from the 2kb aprom. mov chpcon,#81h hardware reset to re-boot from new 2 kb aprom. (s/w reset is invalid in f02k boot mode) setting timer and enable timer interrupt for wake-up . (50us for program operation) end executing new code from address 00h in the 2kb aprom. part 2: procedure of updating the 2kb aprom end of programming ? get the parameters of new code (address and data bytes) through i/o ports, uart or other interfaces . setting control registers for programming: mov sfrah,#address_h mov sfral,#address_l mov sfrfd,#data mov sfrcn,#21h is currently in the f02k boot mode ? no yes no yes read_compay_id read_device_id read_vt read_dist ease 14k ap programming: mov erpage,#01 mov sfrcn,#22h
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 67 - revision a10 19 config bits during the on-chip flash eprom operation mode, the flash eprom can be programmed and veri- fied repeatedly. until the code inside the flash eprom is confirmed ok, the code can be protected. the protection of flash eprom and thos e operations on it are described below. the w78e054d/w78e052d/w78e051d has a special se tting register, the config bits, which cannot be accessed in normal mode. the security regi ster can only be accessed from the flash eprom op- eration mode. those bits of the security regi sters cannot be changed once they have been pro- grammed from high to low. they can only be reset th rough erase-all operation. the security register is addressed in the flash eprom operation mode by address #0ffffh.
w78e054d/w78e052d/w78e051d data sheet - 68 - bit 0: lock bits 0: lock enable 1: lock disable this bit is used to protect the customer's pr ogram code in the w78e054d/w78e052d/w78e051d. it may be set after the programmer finishes the progra mming and verifies sequence. once these bits are set to logic 0, both the flash data and special setting registers cannot be accessed again. bit 1: movc inhibit 0: movc inhibit enable 1: movc inhibit disable this bit is used to restrict the accessible region of the movc instruction. it can prevent the movc in- struction in external program memory from reading the internal program code. when this bit is set to logic 0, a movc instruction in external program memory space will be able to access code only in the external memory, not in the internal memory. a mo vc instruction in internal program memory space will always be able to access the rom data in both internal and external memory. if this bit is logic 1, there are no restrictions on the movc instruction. bit 2: cbs config boot select at power-on reset and external reset. cbs=1: boot from aprom block (default). cbs=0: boot from ldrom block (0x3800). bit 3: nsr (noise sensitivity reduction) nsr=1: noise sensitivity reduction is disabled. nsr=0: noise sensitivity reduction is enabled. bit 4: must be ?1? bit 5: machine cycle select this bit is select mcu core, default value is logic 1, and the mcu core is 12t per instruction. once this bit is set to logic 0, the mcu core is 6t per instruction. bit 6: must be ?1? bit 7: crystal select 0 (24mhz): if system clock is slower than 24mhz, programming ?0?. it can reduce emi effect and save the power consumption. 1 (40mhz): if system clock is fa ster than 24mhz, programming ?1?.
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 69 - revision a10 20 electrical characteristics 20.1 absolute maximum ratings symbol parameter min max unit dc power supply v dd ? v ss 2.4 5.5 v input voltage v in v ss -0.3 v dd +0.3 v operating temperature (w78e054d/w78e052d/w78 e051d) t a -40 +85 c note: exposure to conditions beyond those listed un der absolute maximum ratings may adversely af- fects the lift and reliability of the device.
w78e054d/w78e052d/w78e051d data sheet - 70 - 20.2 dc electrical characteristics t a =-40 ~+85 , v dd =2.4v~5.5v, v ss =0v sym parameter test condition min typ *1 max unit v il input low voltage (ports 0~4, /ea, xtal1, rst) 2.4 < v dd < 5.5v -0.5 0.2v dd -0.1 v v ih input high voltage (ports 0~4, /ea) 2.4 < v dd < 5.5v 0.2v dd +0.9 v dd + 0.5 v v ih1 input high voltage (xtal1, rst) 2.4 < v dd < 5.5v 0.7v dd v dd + 0.5 v v ol output low voltage (ports 0~4, ale, /psen) v dd =4.5v, i ol = 12.0ma *3,*4 v dd =2.4v, i ol = 10ma *3,*4 0.4 v v oh1 output high voltage (ports 1~4) v dd =4.5v, i oh = -300 a *4 v dd =2.4v, i oh = -35 a *4 2.4 2.0 v v oh2 output high voltage (ports 0 & 2 in external bus mode, ale, /psen) v dd =4.5v, i oh = -8.0ma *4 v dd =2.4v, i oh = -2.2ma *4 2.4 2.0 v i il logical 0 input current (ports 1~4) v dd =5.5v, v in =0.4v -45 -50 a i tl logical 1-to-0 transition current (ports 1~4) *2 v dd =5.5v, v in =2.0v -510 -650 a i li input leakage current (port 0) 0 < v in < v dd +0.5 0.1 10 a active mode *5 @12mhz, v dd =5.0v @40mhz, v dd =5.0v @12mhz, v dd =3.3v @20mhz, v dd =3.3v 9.5 16.0 3.1 3.7 ma idle mode @12mhz, v dd =5.0v @40mhz, v dd =5.0v @12mhz, v dd =3.3v @20mhz, v dd =3.3v 3.5 9.2 1.2 1.7 ma i dd power supply current power-down mode <1 50 a r rst rst-pin internal pull- down resistor 2.4 < v dd < 5.5v 100 225 k ? note: *1: typical values are not guaranteed. the values li sted are tested at room temperature and based on
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 71 - revision a10 a limited number of samples. *2: pins of ports 1~4 source a transition current when they are being externally driven from 1 to 0. the transition current reaches its maximum value when v in is approximately 2v. *3: under steady state (non -transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 20ma maximum i ol per 8-bit port: 40ma maximum total i ol for all outputs: 100ma *4: if i oh exceeds the test condition, v oh will be lower than the listed specification. if i ol exceeds the test condition, v ol will be higher than the listed specification. *5: tested while cpu is kept in reset state and ea=h, port0=h. voltage max. frequency 6t/12t mode note 4.5-5.5v 40mhz 12t 4.5-5.5v 20mhz 6t 2.4v 20mhz 12t 2.4v 10mhz 6t frequency vs voltage table 20.3 ac electrical characteristics the ac specifications are a function of the particular process used to manufacture the part, the ratings of the i/o buffers, the capacitive load, and the inter nal routing capacitance. most of the specifications can be expressed in terms of multiple input clock periods (tcp), and actual parts will usually experi- ence less than a 20 ns variation. 20.3.1 clock input waveform t t xtal1 f ch cl op, t cp parameter symbol min. typ. max. unit notes operating speed fop 0 - 40 mhz 1 clock period tcp 25 - - ns 2 clock high tch 10 - - ns 3 clock low tcl 10 - - ns 3 notes: 1. the clock may be stopped indefinitely in either state. 2. the tcp specification is used as a reference in other specifications.
w78e054d/w78e052d/w78e051d data sheet - 72 - 3. there are no duty cycle requirements on the xtal1 input. 20.3.2 program fetch cycle parameter symbol min. typ. max. unit notes address valid to ale low taas 1 tcp - - - ns 4 address hold from ale low taah 1 tcp - - - ns 1, 4 ale low to psen low tapl 1 tcp - - - ns 4 psen low to data valid tpda - - 2 tcp ns 2 data hold after psen high tpdh 0 - 1 tcp ns 3 data float after psen high tpdz 0 - 1 tcp ns ale pulse width talw 2 tcp - 2 tcp - ns 4 psen pulse width tpsw 3 tcp - 3 tcp - ns 4 notes: 1. p0.0 ? p0.7, p2.0 ? p2.7 remains stable throughout entire memory cycle. 2. memory access time is 3 tcp. 3. data have been latched internally prior to psen going high. 4. " " (due to buffer driving delay and wire loading) is 20 ns. 20.3.3 data read cycle parameter symbol min. typ. max. unit notes ale low to rd low tdar 3 tcp - - 3 tcp + ns 1, 2 rd low to data valid tdda - - 4 tcp ns 1 data hold from rd high tddh 0 - 2 tcp ns data float from rd high tddz 0 - 2 tcp ns rd pulse width tdrd 6 tcp - 6 tcp - ns 2 notes: 1. data memory access time is 8 tcp. 2. " " (due to buffer driving delay and wire loading) is 20 ns. 20.3.4 data write cycle parameter symbol min. typ. max. unit
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 73 - revision a10 ale low to wr low tdaw 3 tcp - - 3 tcp + ns data valid to wr low tdad 1 tcp - - - ns data hold from wr high tdwd 1 tcp - - - ns wr pulse width tdwr 6 tcp - 6 tcp - ns note: " " (due to buffer driving delay and wire loading) is 20 ns. 20.3.5 port access cycle parameter symbol min. typ. max. unit port input setup to ale low tpds 1 tcp - - ns port input hold from ale low tpdh 0 - - ns port output to ale tpda 1 tcp - - ns note: ports are read during s5p2, and output data be comes available at the end of s6p2. the timing data are referenced to ale, since it provides a convenient reference. 20.3.6 program operation parameter symbol min. typ. max. unit vpp setup time tvps 2.0 - - s data setup time tds 2.0 - - s data hold time tdh 2.0 - - s address setup time tas 2.0 - - s address hold time tah 0 - - s ce program pulse width for pro- gram operation tpwp 290 300 310 s oectrl setup time tocs 2.0 - - s oectrl hold time toch 2.0 - - s oe setup time toes 2.0 - - s oe high to output float tdfp 0 - 130 ns data valid from oe toev - - 150 ns note: flash data can be accessed only in flash mode. the rst pin must pull in vih status, the ale pin must pull in vil status, and the psen pin must pull in vih status.
w78e054d/w78e052d/w78e051d data sheet - 74 - 20.4 timing waveforms 20.4.1 program fetch cycle s1 xtal1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 ale port 2 a0-a7 a0-a7 data a0-a7 code t a0-a7 data code port 0 psen pdh, t pdz t pda t aah t aas t psw t apl t alw 20.4.2 data read cycle s2 s3 s5 s6 s1 s2 s3 s4 s1 s5 s6 s4 xtal1 ale psen a8-a15 data out port 2 port 0 a0-a7 wr t t daw dad t dwr t dwd
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 75 - revision a10 20.4.3 data write cycle s2 s3 s5 s6 s1 s2 s3 s4 s1 s5 s6 s4 xtal1 ale psen a8-a15 data out port 2 port 0 a0-a7 wr t t daw dad t dwr t dwd 20.4.4 port access cycle xtal1 ale s5 s6 s1 data out t t port input t sample pda pdh pds
w78e054d/w78e052d/w78e051d data sheet - 76 - 20.4.5 reset pin access cycle v ss v dd pof internal reset power 1 = reset state 0 = cpu free running ~0.7v reset pin ale crystal clock 65536 crystal clock ~2.0v 12 crystal clock = 1 machine cycle 24 crystal clock
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 77 - revision a10 21 application circuits 21.1 external program memory and crystal a9 a11 psen a1 vcc ad2 rst a8 r a3 a13 a12 c2 64kb rom 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 1 20 22 11 12 13 15 16 17 18 19 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 ce oe o0 o1 o2 o3 o4 o5 o6 o7 ad5 ad5 ad4 c1 ad7 ad3 a10 ad1 74373 3 2 4 5 7 6 8 9 13 12 14 15 17 16 18 19 1 11 d0 q0 d1 q1 d2 q2 d3 q3 d4 q4 d5 q5 d6 q6 d7 q7 oc g ad2 a15 a14 ad1 a7 ale a4 crystal a11 vcc ad5 a6 a2 a0 ad6 ad4 a12 w78e054ddg-40dip 31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 20 40 ea xta l1 xta l2 rst p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p1.0/t2 p1.1/t2ex p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd/p3.7 wr/p3.6 psen ale txd / p3. 1 rxd/p3.0 vss vdd a8 a5 a1 a6 w78e052ddg-40dip w78e051ddg-40dip a4 10uf a0 ad7 a2 ad2 ad3 a15 a14 a3 a10 ad7 a9 ad6 ad1 ad0 a5 a13 ad4 ad6 ad3 ad0 8.2k a7 ad0 figure a 21.2 expanded external data memory and oscillator 64kb ram 12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 13 14 15 17 18 19 20 21 22 30 24 29 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 d0 d1 d2 d3 d4 d5 d6 d7 cs1 cs2 oe we ad7 a13 a10 ad4 a12 a7 8.2k a15 a13 ad2 a5 a6 10uf a1 ad5 a8 a3 a2 ale ad6 ad1 a12 a15 a4 a8 a5 vcc rst ad0 a10 ad1 a4 ad1 ad6 /wr vcc ad7 a14 ad6 74373 3 2 4 5 7 6 8 9 13 12 14 15 17 16 18 19 1 11 d0 q0 d1 q1 d2 q2 d3 q3 d4 q4 d5 q5 d6 q6 d7 q7 oc g w78e052ddg-40dip w78e051ddg-40dip a14 vcc ad5 a6 ad2 ad4 a7 a2 ad4 /rd ad5 a9 ad7 ad3 a0 a11 a9 a1 oscillator a0 ad3 vcc ad0 a11 ad3 ad2 a3 ad0 w78e054ddg-40dip 31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 20 40 ea xta l 1 xta l 2 rst p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p1.0/t2 p1.1/t2ex p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd/p3.7 wr/p3.6 psen ale txd / p3. 1 rxd/p3.0 vss vdd figure b
w78e054d/w78e052d/w78e051d data sheet - 78 - 21.3 internal program memory and oscillator for eft application ad6 ad4 a12 ad5 8.2k ad4 10uf ad7 a3 ad1 vcc a9 ad5 ad0 a6 ad2 a15 a15 a0 a0 a6 a12 ad3 a10 rst a1 a9 a5 ad2 a11 ad3 w78e054ddg-40dip ea 31 xta l 1 19 xta l 2 18 rst 9 p3.2/int0 12 p3.3/int1 13 p3.4/t0 14 p3.5/t1 15 p1.0/t2 1 p1.1/t2ex 2 p1.2 3 p1.3 4 p1.4 5 p1.5 6 p1.6 7 p1.7 8 p0.0 39 p0.1 38 p0.2 37 p0.3 36 p0.4 35 p0.5 34 p0.6 33 p0.7 32 p2.0 21 p2.1 22 p2.2 23 p2.3 24 p2.4 25 p2.5 26 p2.6 27 p2.7 28 rd/p3.7 17 wr/p3.6 16 psen 29 ale 30 txd / p3. 1 11 rxd/p3.0 10 vss 20 vdd 40 a4 ad5 ad0 ad3 ad1 a13 ad7 a1 a8 ad7 ale a11 ad1 ad6 a2 a10 74373 d0 3 q0 2 d1 4 q1 5 d2 7 q2 6 d3 8 q3 9 d4 13 q4 12 d5 14 q5 15 d6 17 q6 16 d7 18 q7 19 oc 1 g 11 ad4 a14 ad0 a14 a5 a13 a3 a7 a7 a8 ad6 vcc a2 ad2 a4 64kb ram a0 12 a1 11 a2 10 a3 9 a4 8 a5 7 a6 6 a7 5 a8 27 a9 26 a10 23 a11 25 a12 4 a13 28 a14 3 a15 31 d0 13 d1 14 d2 15 d3 17 d4 18 d5 19 d6 20 d7 21 cs1 22 cs2 30 oe 24 we 29 /wr /rd vcc w78e052ddg-40dip w78e051ddg-40dip cry stal r c2 c1 10k figure c 21.4 reference value of xtal crystal c1 c2 r 6 mhz 68p 68p - 16 mhz 47p 47p - 24 mhz 20p 20p - 32 mhz 10p 10p 6.8k 40 mhz 5p 5p 4.7k above table shows the reference values for crystal applications . notes: 1. c1, c2, r c omponents refer to figure a,c 2. crystal layout must get close to xtal1 and xtal2 pins on us er's application board.
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 79 - revision a10 22 application note in-system programming software examples this application note illustrates the in-system programmability of the mi crocontroller. in this example, microcontroller will boot from 2k ldrom bank enter in-system programming mode for programming the contents of aprom, this sample to erase aprom, erase verify aprom, read one byte for aprom, write one byte for aprom, read cid/did. . example: base on keil c51 compiler $nomod51 #include eapage data 0beh chpcon data 0bfh sfral data 0c4h sfrah data 0c5h sfrfd data 0c6h sfrcn data 0c7h ;cpu clock = 12mhz/12t mode read_time equ 1 program_time equ 50 erase_time equ 5000 ;for w78e(i)054d aprom_end_address equ 03800h ;for w78e(i)052d ;aprom_end_address equ 02000h ;for w78e(i)051d ;aprom_end_address equ 01000h flash_standby equ 00111111b read_cid equ 00001011b read_did equ 00001100b erase_rom equ 00100010b erase_verify equ 00001001b program_rom equ 00100001b program_verify_rom equ 00001010b read_rom equ 00000000b org 03800h mov sp,#060h
w78e054d/w78e052d/w78e051d data sheet - 80 - mov tmod,#01h ;set timer0 as mode1 call read_company_id call read_device_id_high call read_device_id_low call erase_aprom call erase_verify_rom call program_aprom call program_verify_aprom call software_reset sjmp $ ;************************************************************************ ; * read_company_id ;************************************************************************ read_company_id: mov sfrcn,#read_cid mov tl0,#low (65536-read_time) mov th0,#high(65536-read_time) setb tr0 mov chpcon,#00000011b clr tf0 clr tr0 mov a,sfrfd ;check read company id cjne a,#0dah,cid_error ret cid_error: mov p1,#01h sjmp $ ;************************************************************************ ; * read device id high ;************************************************************************ read_device_id_high: mov sfral,#0ffh mov sfrah,#0ffh mov sfrcn,#read_did mov tl0,#low (65536-read_time) mov th0,#high(65536-read_time) setb tr0 mov chpcon,#00000011b clr tf0 clr tr0 mov a,sfrfd ;read device id high byte ret ;************************************************************************* ; * read device id low
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 81 - revision a10 ;************************************************************************* read_device_id_low: mov sfral,#0feh mov sfrah,#0ffh mov sfrcn,#read_did mov tl0,#low (65536-read_time) mov th0,#high(65536-read_time) setb tr0 mov chpcon,#00000011b clr tf0 clr tr0 mov a,sfrfd ;read device id low byte ret ;************************************************************************ ;* flash standby mode ;************************************************************************ standby: mov sfrcn,#flash_standby mov sfrfd,#0ffh mov sfral,#0ffh mov sfrah,#0ffh setb tr0 mov chpcon,#00000011b clr tf0 clr tr0 ret ;************************************************************************ ;* erase aprom ;************************************************************************ erase_aprom: mov eapage,#01h ;set eapage is aprom mov sfrcn,#erase_rom mov tl0,#low (65536-erase_time) mov th0,#high(65536-erase_time) setb tr0 mov chpcon,#00000011b mov eapage,#00h ;clear eapage clr tf0 clr tr0 ret ;************************************************************************ ; * verify aprom bank ;************************************************************************
w78e054d/w78e052d/w78e051d data sheet - 82 - erase_verify_rom: mov sfrcn,#erase_verify mov dptr,#0000h er_lp: mov tl0,#low (65536-read_time) mov th0,#high(65536-read_time) mov sfral,dpl mov sfrah,dph setb tr0 mov chpcon,#00000011b clr tf0 clr tr0 mov a,sfrfd cjne a,#0ffh,erase_verify_error inc dptr mov r0,dpl cjne r0,#low (aprom_end_address),er_lp mov r1,dph cjne r1,#high(aprom_end_address),er_lp ret erase_verify_error: mov p1,#02h sjmp $ ;************************************************************************** ;*programming aprom bank, aprom write 55h,aah,55h,aah........ ;************************************************************************** program_aprom: mov sfrcn,#program_rom mov dptr,#0000h mov a,#055h wr_lp: mov th0,#high(65536-program_time) mov tl0,#low (65536-program_time) mov sfrfd,a mov sfral,dpl mov sfrah,dph setb tr0 mov chpcon,#00000011b clr tf0 clr tr0 cpl a inc dptr mov r0,dpl cjne r0,#low (aprom_end_address),wr_lp
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 83 - revision a10 mov r1,dph cjne r1,#high(aprom_end_address),wr_lp ret ;************************************************************************** ;*program verify aprom bank, read aprom 55h,aah,55h,aah........ ;************************************************************************** program_verify_aprom: mov sfrcn,#program_verify_rom mov dptr,#0000h mov b,#055h rd_lp: mov th0,#high(65536-read_time) mov tl0,#low (65536-read_time) mov sfral,dpl mov sfrah,dph setb tr0 mov chpcon,#00000011b clr tf0 clr tr0 mov a,sfrfd cjne a,b,program_fail mov a,b cpl a mov b,a inc dptr mov r0,dpl cjne r0,#low (aprom_end_address),rd_lp mov r1,dph cjne r1,#high(aprom_end_address),rd_lp ret program_fail: mov p1,#03h sjmp $ ;************************************************************************** ;* programming completly, software reset cpu to aprom ;************************************************************************** software_reset: mov chpcon,#081h ;chpcon=081h, software reset to aprom. sjmp $ end
w78e054d/w78e052d/w78e051d data sheet - 84 - 23 package dimensions 23.1 40-pin dip 1.37 1.22 0.054 0.048 symbol min nom max max nom min dimension in inch dimension in mm a b c d e a l s a a 1 2 e 0.050 1.27 0.210 5.33 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.41 0.25 3.94 0.46 4.06 0.56 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.540 0.550 0.545 13.72 13.97 13.84 17.02 15.24 14.99 15.49 0.600 0.590 0.610 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 2.055 2.070 52.20 52.58 015 0.090 2.29 0.650 0.630 16.00 16.51 15 0 seating plane e a 2 a c e base plane 1 a 1 e l a s 1 e d 1 b b 40 21 20 1
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 85 - revision a10 23.2 44-pin plcc 44 40 39 29 28 18 17 7 61 l c 1 b 2 a h d d e b eh e y a a 1 seating plane d g g e symbol min nom max max nom min dimension in inch dimension in mm a b c d e h e l y a a 1 2 e b 1 h d g g d e 0.020 0.145 0.026 0.016 0.008 0.648 0.590 0.680 0.090 0.150 0.028 0.018 0.010 0.653 0.610 0.690 0.100 0.050 bsc 0.185 0.155 0.032 0.022 0.014 0.658 0.630 0.700 0.110 0.004 0.51 3.68 0.66 0.41 0.20 16.46 14.99 17.27 2.29 3.81 0.71 0.46 0.25 16.59 15.49 17.53 2.54 1.27 4.70 3.94 0.81 0.56 0.36 16.71 16.00 17.78 2.79 0.10 bsc 16.71 16.59 16.46 0.658 0.653 0.648 16.00 15.49 14.99 0.630 0.610 0.590 17.78 17.53 17.27 0.700 0.690 0.680
w78e054d/w78e052d/w78e051d data sheet - 86 - 23.3 44-pin pqfp 0.25 0.10 0.010 0.004 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 0.006 0.15 - - 0.002 0.075 0.01 0.081 0.014 0.087 0.018 1.90 0.25 0.05 2.05 0.35 2.20 0.45 0.390 0.510 0.025 0.063 0.004 0 10 0.394 0.520 0.031 0.398 0.530 0.037 9.9 0.80 12.95 0.65 1.60 10.00 13.20 0.8 10.1 13.45 0.95 0.398 0.394 0.390 0.530 0.520 0.510 13.45 13.20 12.95 10.1 10.00 9.9 10 0 0.10 .0315 0.01 0.02 0.25 0.5 seating plane 11 22 12 see detail f e b a y 1 a a 2 l l 1 c e e h 1 d 44 h d 34 33 detail f
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 87 - revision a10 23.4 48-pin lqfp
w78e054d/w78e052d/w78e051d data sheet - 88 - 24 revision history version date page description a01 august 14, 2008 - initial issued a02 november 3,2008 - update dc table typing error. a03 december 15,2008 - update config bit table, and isp boot a04 january 7,2007 70 update v il and v ih . a05 march 9, 2009 43 update soft reset, only ld jump to ap function. a06 march 20, 2009 18 - - 1. rename sfr register por (0x86h) to p0upr. 2. revise some typing errors in data sheet. 3. update dc table a07 april 22, 2009 68 1. revise type application circuit in data sheet. a08 june 30, 2009 30 61 81 all pages 1. add the isp control table. 2. revise content of char. 17. 3. modify the isp demo code. 4. remove the ?preliminary? character for each page. a09 dec 30, 2009 68 77 1. revise the ?config bits? description for bit4, bit6 and bit7. 2. add the timing for external reset pin. a10 oct 20, 2011 28 70 1. revised the chpcon description 2. added description for ?21.4 reference value of xtal
w78e054d/w78e052d/w78e051d data sheet publication release date: oct 20, 2011 - 89 - revision a10 important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed, ?insecure usage?. insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dy- namic, brake or safety systems designed for vehicu lar use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customer?s risk, and in the event that third parties lay claims to nuvoton as a result of customer?s insecure usage, customer shall indemnify the damages and liabilities thus incurred by nuvoton.

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